LF411ACN/NOPB National Semiconductor, LF411ACN/NOPB Datasheet - Page 8

• Manufacturer Part Number: LF411ACN/NOPB
• Description: IC OP AMP LOW JFET INPUT 8-DIP
• Manufacturer: National Semiconductor
• Series: BI-FET II™r

Specifications of LF411ACN/NOPB

• Amplifier Type: J-FET
• Number Of Circuits: 1
• Slew Rate: 15 V/µs
• Gain Bandwidth Product: 4MHz
• Current - Input Bias: 50pA
• Voltage - Input Offset: 300µV
• Current - Supply: 1.8mA
• Voltage - Supply, Single/dual (±): 10 V ~ 44 V, ±5 V ~ 22 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Bandwidth: 4 MHz
• Common Mode Rejection Ratio: 100
• Current, Input Bias: 50 pA
• Current, Input Offset: 25 pA
• Current, Output: 25 mA
• Current, Supply: 1.8 mA
• Harmonic Distortion: 0.02 %
• Impedance, Thermal: 162 °C/W
• Number Of Amplifiers: Single
• Package Type: MDIP-8
• Power Dissipation: 670 mW
• Resistance, Input: 10^12 Ohms
• Temperature, Operating, Range: 0 to +70 °C
• Voltage, Gain: 200 V/mV
• Voltage, Input: 10 to 44 V
• Voltage, Noise: 25 nV/sqrt Hz
• Voltage, Offset: 0.3 mV
• Voltage, Output, High: 13.5 V
• Voltage, Output, Low: -13.5 V
• Voltage, Supply: ±19 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output Type: -
• Current - Output / Channel: -
• -3db Bandwidth: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device
• Other names: *LF411ACN; *LF411ACN/NOPB; LF411ACN

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Pulse Response
Application Hints
The LF411 series of internally trimmed JFET input op amps
( BI-FET II
guaranteed input offset voltage drift. These JFETs have
large reverse breakdown voltages from gate to source and
drain eliminating the need for clamps across the inputs.
Therefore, large differential input voltages can easily be
accommodated without a large increase in input current. The
maximum differential input voltage is independent of the
supply voltages. However, neither of the input voltages
should be allowed to exceed the negative supply as this will
cause large currents to flow which can result in a destroyed
unit.
Exceeding the negative common-mode limit on either input
will force the output to a high state, potentially causing a
reversal of phase to the output. Exceeding the negative
common-mode limit on both inputs will force the amplifier
output to a high state. In neither case does a latch occur
since raising the input back within the common-mode range
again puts the input stage and thus the amplifier in a normal
operating mode.
Exceeding the positive common-mode limit on a single input
will not change the phase of the output; however, if both
inputs exceed the limit, the output of the amplifier may be
forced to a high state.
The amplifier will operate with a common-mode input voltage
equal to the positive supply; however, the gain bandwidth
and slew rate may be decreased in this condition. When the
negative common-mode voltage swings to within 3V of the
negative supply, an increase in input offset voltage may
occur.
The LF411 is biased by a zener reference which allows
normal circuit operation on
voltages less than these may result in lower gain bandwidth
and slew rate.
™
) provide very low input offset voltage and
R
±
L
4.5V power supplies. Supply
=2 kΩ, C
L
10 pF (Continued)
Current Limit (R
8
The LF411 will drive a 2 kΩ load resistance to
full temperature range. If the amplifier is forced to drive
heavier load currents, however, an increase in input offset
voltage may occur on the negative voltage swing and finally
reach an active current limit on both positive and negative
swings.
Precautions should be taken to ensure that the power supply
for the integrated circuit never becomes reversed in polarity
or that the unit is not inadvertently installed backwards in a
socket as an unlimited current surge through the resulting
forward diode within the IC could cause fusing of the internal
conductors and result in a destroyed unit.
As with most amplifiers, care should be taken with lead
dress, component placement and supply decoupling in order
to ensure stability. For example, resistors from the output to
an input should be placed with the body close to the input to
minimize “pick-up” and maximize the frequency of the feed-
back pole by minimizing the capacitance from the input to
ground.
A feedback pole is created when the feedback around any
amplifier is resistive. The parallel resistance and capacitance
from the input of the device (usually the inverting input) to AC
ground set the frequency of the pole. In many instances the
frequency of this pole is much greater than the expected
3 dB frequency of the closed loop gain and consequently
there is negligible effect on stability margin. However, if the
feedback pole is less than approximately 6 times the ex-
pected 3 dB frequency, a lead capacitor should be placed
from the output to the input of the op amp. The value of the
added capacitor should be such that the RC time constant of
this capacitor and the resistance it parallels is greater than or
equal to the original feedback pole time constant.
L
=100Ω)
00565543
±
10V over the