MCP6284-E/SL Microchip Technology, MCP6284-E/SL Datasheet - Page 13

• Manufacturer Part Number: MCP6284-E/SL
• Description: IC OPAMP 2.2V QUAD R-R 14SOIC
• Manufacturer: Microchip Technology

Specifications of MCP6284-E/SL

• Slew Rate: 2.5 V/µs
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Amplifier Type: General Purpose
• Number Of Circuits: 4
• Output Type: Rail-to-Rail
• Gain Bandwidth Product: 5MHz
• Current - Input Bias: 1pA
• Voltage - Input Offset: 3000µV
• Current - Supply: 450µA
• Current - Output / Channel: 25mA
• Voltage - Supply, Single/dual (±): 2.2 V ~ 6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Channels: 4
• Common Mode Rejection Ratio (min): 70 dB
• Input Offset Voltage: 3 mV
• Input Bias Current (max): 1 pA
• Operating Supply Voltage: 3 V, 5 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Shutdown: No
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.2 V
• Technology: CMOS
• Voltage Gain Db: 110 dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• -3db Bandwidth: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.2
The output voltage range of the MCP6281/1R/2/3/4/5
op amp is V
when R
V
4.3
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. A unity-gain buffer (G = +1) is the most
sensitive to capacitive loads, though all gains show the
same general behavior.
When driving large capacitive loads with these op
amps (e.g., > 100 pF when G = +1), a small series
resistor at the output (R
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will generally be lower than the bandwidth
with no capacitive load.
FIGURE 4-3:
stabilizes large capacitive loads.
Figure 4-4
ent capacitive loads and gains. The x-axis is the
normalized load capacitance (C
circuit's noise gain. For non-inverting gains, G
Signal Gain are equal. For inverting gains, G
1+|Signal Gain| (e.g., -1 V/V gives G
FIGURE 4-4:
for Capacitive Loads.
© 2008 Microchip Technology Inc.
DD
V
IN
= 5.5V. Refer to
1,000
100
10
Rail-to-Rail Output
Capacitive Loads
L
10
= 10 kΩ is connected to V
gives recommended R
DD
Normalized Load Capacitance; C
MCP628X
+
–
– 15 mV (min.) and V
Figure 2-16
100
Output Resistor, R
Recommended R
ISO
in
Figure
G
G
G
R
N
N
N
L
ISO
= 1 V/V
= 2 V/V
/G
for more information.
ISO
4 V/V
1,000
C
N
SS
), where G
N
L
4-3) improves the
values for differ-
= +2 V/V).
+ 15 mV (max.)
L
/ G
ISO
ISO
N
DD
(pF)
N
10,000
Values
/2 and
V
and the
N
OUT
is the
N
is
After selecting R
resulting frequency response peaking and step
response overshoot. Modify R
response is reasonable. Bench evaluation and simula-
tions with the MCP6281/1R/2/3/4/5 SPICE macro
model are helpful.
4.4
The MCP6283 and MCP6285 are single and dual op
amps with Chip Select (CS), respectively. When CS is
pulled high, the supply current drops to 0.7 µA (typical)
and flows through the CS pin to V
pens, the amplifier output is put into a high-impedance
state. By pulling CS low, the amplifier is enabled. The
CS pin has an internal 5 MΩ (typical) pull-down resistor
connected to V
floating.
supply current response to a CS pulse.
4.5
The MCP6285 is a dual op amp with Chip Select (CS).
The Chip Select input is available on what would be the
non-inverting input of a standard dual op amp (pin 5).
This pin is available because the output of op amp A
connects to the non-inverting input of op amp B, as
shown in
be connected to a microcontroller I/O line, puts the
device in Low-power mode. Refer to Section 4.4
“MCP628X Chip Select (CS)”.
FIGURE 4-5:
The output of op amp A is loaded by the input imped-
ance of op amp B, which is typically 10
specified in the DC specification table (Refer to
Section 4.3 “Capacitive Loads” for further details
regarding capacitive loads).
The common mode input range of these op amps is
specified in the data sheet as V
V
is limited to V
10 kΩ load), the non-inverting input range of op amp B
is limited to the common mode input range of
V
V
V
DD
SS
MCP6281/1R/2/3/4/5
INA
INA
+ 20 mV and V
+ 300 mV. However, since the output of op amp A
+
–
MCP628X Chip Select (CS)
Cascaded Dual Op Amps
(MCP6285)
2
3
Figure 1-1
Figure
OL
A
SS
V
4-5. The Chip Select input, which can
and V
ISO
OUTA
, so it will go low if the CS pin is left
DD
1
for your circuit, double-check the
shows the output voltage and
MCP6285
/V
Cascaded Gain Amplifier.
– 20 mV.
OH
INB
CS
(20 mV from the rails with a
+
5
V
INB
ISO
6
–
SS
's value until the
SS
DS21811E-page 13
. When this hap-
B
– 300 mV and
13
Ω || 6 pF, as
7
V
OUTB