MCP6141-I/P Microchip Technology, MCP6141-I/P Datasheet - Page 12
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MCP6141-I/P
Manufacturer Part Number
MCP6141-I/P
Description
IC OPAMP 1.4V SINGLE R-R 8-DIP
Manufacturer
Microchip Technology
Specifications of MCP6141-I/P
Slew Rate
0.003 V/µs
Amplifier Type
General Purpose
Number Of Circuits
1
Output Type
Rail-to-Rail
Gain Bandwidth Product
100kHz
Current - Input Bias
1pA
Voltage - Input Offset
3000µV
Current - Supply
0.6µA
Current - Output / Channel
20mA
Voltage - Supply, Single/dual (±)
1.4 V ~ 6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Through Hole
Package / Case
8-DIP (0.300", 7.62mm)
Op Amp Type
Non Unity Gain Stable
No. Of Amplifiers
1
Bandwidth
100kHz
Supply Voltage Range
1.4V To 5.5V
Amplifier Case Style
DIP
No. Of Pins
8
Number Of Channels
1
Voltage Gain Db
115 dB
Common Mode Rejection Ratio (min)
60 dB
Input Offset Voltage
3 mV
Operating Supply Voltage
3 V, 5 V
Supply Current
0.001 mA
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
-3db Bandwidth
-
Lead Free Status / Rohs Status
Details
MCP6141/2/3/4
FIGURE 3-5:
function on the MCP6143 op amp.
3.8
Good PC board layout techniques will help you achieve
the performance shown in the specifications and typical
performance curves. It will also assist in minimizing
Electro-Magnetic Compatibility (EMC) issues.
3.8.1
In applications where low input bias current is critical,
PC board surface leakage effects and signal coupling
from trace to trace need to be considered.
Surface leakage is caused by a difference in voltage
between traces, combined with high humidity, dust or
other contamination on the board. Under low humidity
conditions, a typical resistance between nearby traces
is 10
to flow, which is greater than the input current of the
MCP6141/2/3/4 family at 25°C (1 pA, typ).
The simplest technique to reduce surface leakage is
using a guard ring around sensitive pins (or traces).
The guard ring is biased at the same voltage as the
sensitive pin or trace. Figure 3-6 shows an example of
a typical layout.
FIGURE 3-6:
layout.
21668A-page 12
I
V
I
CS
VSS
I
VDD
CS
OUT
12
5 pA, typ
20 pA, typ
5 pA, typ
. A 5V difference would cause 5 pA of current
Layout Considerations
Hi-Z
Guard Ring
SURFACE LEAKAGE
V
IL
t
ON
IN-
Timing Diagram for the CS
Example of Guard Ring
0.6 µA, typ
0.6 µA, typ
IN+
V
IH
t
V
OFF
5 pA, typ
5 pA, typ
20 pA, typ
SS
Hi-Z
Circuit schematics for different guard ring implementa-
tions are shown in Figure 3-7. Figure 3-7A biases the
guard ring to the input common mode voltage, which is
most effective for non-inverting gains. Figure 3-7B
biases the guard ring to a reference voltage (V
which can be ground), which is useful for inverting
gains and precision photo sensing circuits.
FIGURE 3-7:
connection strategies to reduce surface leakage
effects.
3.8.2
In order to help prevent crosstalk:
• Separate digital components from analog compo-
• Keep sensitive traces short and straight. Separate
• Use a 0.1 µF supply bypass capacitor within 0.1”
Figure 3-7A
Figure 3-7B
nents, and low speed devices from high speed
devices.
them from interfering components and traces.
This is especially important for high frequency
(low rise time) signals.
(2.5 mm) of the V
to the ground plane.
V
REF
COMPONENT PLACEMENT
V
REF
DD
Two possible guard ring
pin. It must connect directly
2002 Microchip Technology Inc.
MCP614X
MCP614X
V
V
DD
DD
REF
,