AD8001AR-REEL7 Analog Devices Inc, AD8001AR-REEL7 Datasheet - Page 14

• Manufacturer Part Number: AD8001AR-REEL7
• Description: IC OPAMP CF LP LDIST 70MA 8SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD8001AR-REEL7

• Rohs Status: RoHS non-compliant
• Amplifier Type: Current Feedback
• Number Of Circuits: 1
• Slew Rate: 1200 V/µs
• -3db Bandwidth: 715MHz
• Current - Input Bias: 5µA
• Voltage - Input Offset: 2000µV
• Current - Supply: 5mA
• Current - Output / Channel: 70mA
• Voltage - Supply, Single/dual (±): ±3 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Output Type: -
• Gain Bandwidth Product: -

AD8001
Layout Considerations
The specified high speed performance of the AD8001 requires
careful attention to board layout and component selection. Proper
R
are mandatory.
The PCB should have a ground plane covering all unused portions
of the component side of the board to provide a low impedance
ground path. The ground plane should be removed from the area
near the input pins to reduce stray capacitance.
Chip capacitors should be used for supply bypassing (see Figure 13).
One end should be connected to the ground plane and the other
within 1/8 inch of each power pin. An additional large
Component
R
R
R
R
R
Small Signal
0.1 dB Flatness
F
G
O
S
T
F
(MHz)
(Ω)
BW (MHz)
(Ω)
(Nominal) (Ω) 54.9
(Ω)
(Nominal) (Ω) 49.9
design techniques and low parasitic component selection
IN
Inverting Configuration
R
T
R
G
R
S
–1
649
649
0
340
105
–V
+V
R
Figure 13. Inverting and Noninverting Configurations for Evaluation Boards
S
+1
1050
49.9
49.9
880
70
F
S
AD8001AN (PDIP)
Gain
+2
750
750
49.9
49.9
460
105
R
O
+10
470
51
49.9
49.9
260
OUT
Table I. Recommended Component Values
+100
1000
10
49.9
49.9
20
+V
–V
S
S
Supply Bypassing
–1
604
604
49.9
0
54.9
370
130
C1
0.1 F
C2
0.1 F
–14–
AD8001AR (SOIC)
+1
953
49.9
49.9
710
100
(4.7 µF–10 µF) tantalum electrolytic capacitor should be con-
nected in parallel, but not necessarily so close, to supply current
for fast, large-signal changes at the output.
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance variations of less than 1 pF at the invert-
ing input will significantly affect high speed performance.
Stripline design techniques should be used for long signal traces
(greater than about 1 inch). These should be designed with a
characteristic impedance of 50 Ω or 75 Ω and be properly termi-
nated at each end.
C3
10 F
C4
10 F
Gain
+2
681
681
49.9
49.9
440
120
+10
470
51
49.9
49.9
260
+100
1000
10
49.9
49.9
20
IN
Noninverting Configuration
R
–1
845
845
49.9 49.9
0
54.9 49.9
240
110
G
R
T
AD8001ART (SOT-23-5)
+1
1000 768
795
300
+V
–V
R
F
S
S
768
49.9
49.9
Gain
+2
380
145
R
O
+10
470
51
49.9
49.9
260
OUT
REV. D
+100
1000
10
49.9
49.9
20