AD8230YRZ Analog Devices Inc, AD8230YRZ Datasheet - Page 11

• Manufacturer Part Number: AD8230YRZ
• Description: IC AMP CHOPPER R-R PREC 8SOIC
• Manufacturer: Analog Devices Inc
• Type: Instrumentation Amplifierr

Specifications of AD8230YRZ

• Amplifier Type: Chopper (Zero-Drift)
• Number Of Circuits: 1
• Output Type: Rail-to-Rail
• Slew Rate: 2 V/µs
• Current - Input Bias: 150pA
• Voltage - Input Offset: 20µV
• Current - Supply: 3.2mA
• Current - Output / Channel: 15mA
• Voltage - Supply, Single/dual (±): 8 V ~ 16 V, ±4 V ~ 8 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• No. Of Amplifiers: 1
• Input Offset Voltage: 10µV
• Bandwidth: 2kHz
• Amplifier Output: Rail To Rail
• Cmrr: 120dB
• Supply Voltage Range: 8V To 16V, ± 4V To ± 18V
• Supply Current: 2.7mA
• Rohs Compliant: Yes
• Number Of Channels: 1
• Number Of Elements: 1
• Power Supply Requirement: Single/Dual
• Voltage Gain Db: 60dB
• Single Supply Voltage (typ): 9/12/15V
• Dual Supply Voltage (typ): ±5V
• Power Dissipation: 304mW
• Rail/rail I/o Type: Rail to Rail Input/Output
• Single Supply Voltage (min): 8V
• Single Supply Voltage (max): 16V
• Dual Supply Voltage (min): ±4V
• Dual Supply Voltage (max): ±8V
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 8
• Package Type: SOIC N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• -3db Bandwidth: -
• Gain Bandwidth Product: -
• Lead Free Status / Rohs Status: Compliant

THEORY OF OPERATION
Auto-zeroing is a dynamic offset and drift cancellation
technique that reduces input-referred voltage offset to the
μV level and voltage offset drift to the nV/°C level. A further
advantage of dynamic offset cancellation is the reduction of
low frequency noise, in particular the 1/f component.
The AD8230 is an instrumentation amplifier that uses an
auto-zeroing topology and combines it with high common-
mode signal rejection. The internal signal path consists of an
active differential sample-and-hold stage (preamp) followed by
a differential amplifier (gain amp). Both amplifiers implement
auto-zeroing to minimize offset and drift. A fully differential
topology increases the immunity of the signals to parasitic noise
and temperature effects. Amplifier gain is set by two external
resistors for convenient TC matching.
The signal sampling rate is controlled by an on-chip, 6 kHz
oscillator and logic to derive the required nonoverlapping
clock phases. For simplification of the functional description,
two sequential clock phases, A and B, are shown to distinguish
the order of internal operation, as depicted in Figure 30 and
Figure 31, respectively.
During Phase A, the sampling capacitors are connected to the
inputs. The input signal’s difference voltage, V
across the sampling capacitors, C
capacitors only retain the difference voltage, the common-mode
voltage is rejected. During this period, the gain amplifier is not
connected to the preamplifier so its output remains at the level
set by the previously sampled input signal held on C
shown in Figure 30.
V
+V
V
+V
DIFF
DIFF
CM
CM
V
V
V
V
+IN
Figure 30. Phase A of the Sampling Phase
+IN
Figure 31. Phase B of the Sampling Phase
–IN
–IN
C
C
SAMPLE
SAMPLE
V
V
REF
REF
PREAMP
PREAMP
+
+
–
–
+
+
–
–
SAMPLE
–V
–V
–V
–V
R
. Because the sampling
R
S
S
S
S
G
G
C
C
C
C
HOLD
HOLD
HOLD
HOLD
GAIN AMP
GAIN AMP
DIFF
, is stored
R
R
F
F
HOLD
V
V
OUT
OUT
, as
Rev. B | Page 11 of 16
In Phase B, the differential signal is transferred to the hold
capacitors refreshing the value stored on C
the preamplifier is held at a common-mode voltage determined
by the reference potential, V
able to condition the difference signal and set the output voltage
level. The gain amplifier conditions the updated signal stored
on the hold capacitors, C
SETTING THE GAIN
Two external resistors set the gain of the AD8230. The gain is
expressed in the following equation:
Table 5. Gains Using Standard 1% Resistors
Gain
2
10
50
100
200
500
1000
Figure 32 and Table 5 provide an example of some gain settings.
As Table 5 shows, the AD8230 accepts a wide range of resistor
values. Because the instrumentation amplifier has finite driving
capability, ensure that the output load in parallel with the sum
of the gain setting resistors is greater than 2 kΩ.
Offset voltage drift at high temperature can be minimized by
keeping the value of the feedback resistor, R
to the junction leakage current on the R
of the gain setting resistor on offset voltage drift is shown in
Figure 33. In addition, experience has shown that wire-wound
resistors in the gain feedback loop may degrade the offset
voltage performance.
R
Gain
L
||( R
=
F
R
0 Ω (short)
8.06 kΩ
12.1 kΩ
9.76 kΩ
10 kΩ
49.9 kΩ
100 kΩ
+ R
2(1
10µF
F
G
+
) > 2 kΩ
R
R
G
F
)
Figure 32. Gain Setting
4
5
V
HOLD
0.1µF
AD8230
REF
3
REF
1
.
V
+V
REF
. In this manner, the AD8230 is
R
None
2 kΩ
499 Ω
200 Ω
100 Ω
200 Ω
200 Ω
2
6
S
G
2
–V
R
1
7
G
S
R
G
R
0.1µF
F
G
8
pin, Pin 7. The effect
HOLD
F
, small. This is due
Actual Gain
2
10
50.5
99.6
202
501
1002
. The output of
V
10µF
OUT
AD8230
(1)
(2)