AD8517ART-REEL7 Analog Devices Inc, AD8517ART-REEL7 Datasheet - Page 9
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AD8517ART-REEL7
Manufacturer Part Number
AD8517ART-REEL7
Description
IC OPAMP GP R-R 7MHZ SOT23-5
Manufacturer
Analog Devices Inc
Datasheet
1.AD8517ART-R2.pdf
(12 pages)
Specifications of AD8517ART-REEL7
Rohs Status
RoHS non-compliant
Amplifier Type
General Purpose
Number Of Circuits
1
Output Type
Rail-to-Rail
Slew Rate
8 V/µs
Gain Bandwidth Product
7MHz
Current - Input Bias
450nA
Voltage - Input Offset
1300µV
Current - Supply
900µA
Current - Output / Channel
10mA
Voltage - Supply, Single/dual (±)
1.8 V ~ 6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
SOT-23-5, SC-74A, SOT-25
-3db Bandwidth
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD8517ART-REEL7
Manufacturer:
AD
Quantity:
5 510
Company:
Part Number:
AD8517ART-REEL7
Manufacturer:
AVX
Quantity:
5 510
Part Number:
AD8517ART-REEL7
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Battery
Lead-Acid
Lithium
NiMH
NiCd
Carbon-Zinc
RAIL-TO-RAIL INPUT AND OUTPUT
The AD8517 features an extraordinary rail-to-rail input and
output with supply voltages as low as 1.8 V. With the amplifier’s
supply range set to 1.8 V, the input can be set to 1.8 V p-p,
allowing the output to swing to both rails without clipping. Figure
20 shows a scope picture of both input and output taken at unity
gain, with a frequency of 1 kHz, at V
The rail-to-rail feature of the AD8517 can be observed over the
supply voltage range, 1.8 V to 5 V. Traces are shown offset for
clarity.
V
OUT
V
IN
Table I. Typical Battery Life Voltage Range
IN
V
V
D2
D1
S
IN
=
= 1.8 V p-p
0.9V
ESD
ESD
R1
R3
Nominal
Voltage (V)
2
2.6-3.6
1.2
1.2
1.5
Q3
R9
R7
R5
TIME – 200 s/Div
Q1
D8
D7
Q2
S
I1
I2
= 1.8 V and V
R6
R8
Q4
R4
R10
ESD
ESD
End of Voltage
Discharge (V)
1.8
1.7-2.4
1
1
1.1
D4
R2
D3
IN
C1
= 1.8 V p-p.
IN
Q8
Q5
Q10
I3
Q11
Q6
I4
V
Q9
V
CC
EE
INPUT BIAS CONSIDERATION
The input bias current (I
affects all op amps. I
voltage. This offset voltage is created by I
the negative feedback resistor R
and R
50 mV (V
Obviously the lower R
Using a compensation resistor, R
significantly minimize this effect. With the input bias current mini-
mized, we still need to be aware of the input offset current (I
which will generate a slight offset error. Figure 21 shows three
different configurations to minimize IB-induced offset errors.
Q7
F
I5
V
is 100 kΩ, the corresponding generated offset voltage is
V
V
I
I
I
Q13
OS
I7
R
R
= I
B
B
Q14
= R
= R
R
R
R
B
I6
S
I
I
I
I
R
R11
R
C2
R12
F
F
R
B
Q15
F
F
can generate a somewhat significant offset
).
AD8517
AD8517
AD8517
the lower the generated voltage offset.
I8
R
B
F
) is a nonideal, real-life parameter that
R
R
= R
C3
F
F
R13
D16
S
Q19
UNITY GAIN BUFFER
F
INVERTING CONFIGURATION
NONINVERTING CONFIGURATION
. If I
Q17
B
R14
, as shown in Figure 21, can
AD8517/AD8527
B
C4
is 500 nA (worst case),
B
V
V
V
OUT
OUT
OUT
Q20
Q18
when flowing through
D9
D6
V
V
V
CC
OUT
EE
OS
)