ADM1062ASUZ Analog Devices Inc, ADM1062ASUZ Datasheet - Page 32

• Manufacturer Part Number: ADM1062ASUZ
• Description: IC SUPERVISOR/SEQUENCER 48-TQFP
• Manufacturer: Analog Devices Inc
• Type: Sequencerr

Specifications of ADM1062ASUZ

• Number Of Voltages Monitored: 10
• Output: Programmable
• Voltage - Threshold: Adjustable/Selectable
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• For Use With: EVAL-ADM1062TQEBZ - BOARD EVALUATION FOR ADM1062TQEVAL-ADM1062LFEBZ - BOARD EVALUATION FOR ADM1062LF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Reset: -
• Reset Timeout: -

ADM1062
Block Read
In a block read operation, the master device reads a block of
data from a slave device. The start address for a block read must
have been set previously. In the ADM1062, this is done by a
send byte operation to set a RAM address, or a write byte/word
operation to set an EEPROM address. The block read operation
itself consists of a send byte operation that sends a block read
command to the slave, immediately followed by a repeated start
and a read operation that reads out multiple data bytes, as follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. The master asserts an ACK on SDA.
11. The master receives 32 data bytes.
12. The master asserts an ACK on SDA after each data byte.
13. The master asserts a stop condition on SDA to end
S
1
ADDRESS
SLAVE
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
write bit (low).
The addressed slave device asserts an ACK on SDA.
The master sends a command code that tells the slave
device to expect a block read. The ADM1062 command
code for a block read is 0xFD (1111 1101).
The slave asserts an ACK on SDA.
The master asserts a repeat start condition on SDA.
The master sends the 7-bit slave address followed by the
read bit (high).
The slave asserts an ACK on SDA.
The ADM1062 sends a byte-count data byte that tells the
master how many data bytes to expect. The ADM1062
always returns 32 data bytes (0x20), which is the maximum
allowed by the SMBus Version 1.1 specification.
the transaction.
2
W A
Figure 49. Block Read from the EEPROM or RAM
3
COMMAND 0xFD
(BLOCK READ)
4
5
A
6
S
ADDRESS
SLAVE
7
R A
8
COUNT
BYTE
9
10
A
DATA
DATA
11
32
1
12
A
A
13
Rev. B | Page 32 of 36
P
Error Correction
The ADM1062 provides the option of issuing a packet error
correction (PEC) byte after a write to the RAM, a write to the
EEPROM, a block write to the RAM/EEPROM, or a block read
from the RAM/ EEPROM. This option enables the user to verify
that the data received by or sent from the ADM1062 is correct.
The PEC byte is an optional byte sent after the last data byte has
been written to or read from the ADM1062. The protocol is the
same as a block read for Step 1 to Step 12 and then proceeds as
follows:
13. The ADM1062 issues a PEC byte to the master. The master
14. A NACK is generated after the PEC byte to signal the end
15. The master asserts a stop condition on SDA to end the
Note that the PEC byte is calculated using CRC-8. The frame
check sequence (FCS) conforms to CRC-8 by the polynomial
See the SMBus Version 1.1 specification for details.
An example of a block read with the optional PEC byte is shown
in Figure 50.
S
1
ADDRESS
SLAVE
checks the PEC byte and issues another block read if the
PEC byte is incorrect.
of the read.
transaction.
C(x) = x
2
Figure 50. Block Read from the EEPROM or RAM with PEC
W A
8
3
+ x
COMMAND 0xFD
(BLOCK READ)
2
+ x
4
1
+ 1
5
A
6
S
ADDRESS
SLAVE
7
R A
8
COUNT
BYTE
9
DATA
32
10
A
A
DATA
11
1
PEC
13
12
A
14
A
15
P