LTC1536CMS8 Linear Technology, LTC1536CMS8 Datasheet - Page 6

• Manufacturer Part Number: LTC1536CMS8
• Description: IC PREC TRPL SPPLY MONITOR 8MSOP
• Manufacturer: Linear Technology
• Type: Multi-Voltage Supervisorr

Specifications of LTC1536CMS8

• Number Of Voltages Monitored: 3
• Output: Open Drain or Open Collector
• Reset: Active High/Active Low
• Reset Timeout: 140 ms Minimum
• Voltage - Threshold: 2.985V, 4.725V, Adj
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PIN
LTC1536
V
the IC. Bypass to ground with ≥ 0.1µF ceramic capacitor.
V
output FET when the voltage on V
voltage on V
V
used as a logic input with a 1V threshold. If unused it can
be tied to either V
GND (Pin 4): Ground.
RST (Pin 5): Reset Logic Output. Active high CMOS logic
output, drives high to V
An external pull-down on the RST pin will drive this pin high.
RST (Pin 6): Reset Logic Output. Active low, open-drain
logic output with weak pull-up to V
greater than V
BLOCK
6
CC3
CC5
CCA
U
(Pin 1): 3.3V Sense Input and Power Supply Pin for
(Pin 2): 5V Sense Input. Used as gate drive for RST
(Pin 3): 1V Sense, High Impedance Input. Can be
FUNCTIONS
U
CC3
DIAGRAM
V
V
V
GND
PBR
CC3
CC5
CCA
.
CC3
CC3
8
1
2
3
4
POWER
DETECT
U
or V
when interfacing to 5V logic.
TO
CC3
CC5
TO POWER DETECT
AND V
W
, buffered compliment of RST.
7µA
.
CC
INTERNAL
V
CC3
CC5
CC3
is greater than the
. Can be pulled up
REF
+
–
–
+
+
+
–
+
+
–
–
–
SLOW
SLOW
SLOW
FAST
FAST
FAST
TIMER
PBR
RESET
SOFT RESET
Asserted when one or more of the supplies are below trip
thresholds and held for 200ms after all supplies become
valid. Also asserted after PBR is held low for more than two
seconds and for an additional 200ms after PBR is released.
SRST (Pin 7): “Soft” Reset. Active low, open-drain logic
output with weak pull-up to V
than V
after PBR is held low for less than two seconds and released.
PBR (Pin 8): Pushbutton Reset. Active low logic input with
weak pull-up to V
when interfacing to 5V logic. When asserted for less than
two seconds, outputs a soft reset 100µs pulse on the SRST
pin. When PBR is asserted for greater than two seconds,
the RST output is forced low and remains low until 200ms
after PBR is released.
GENERATOR
CC3
200ms
RESET
when interfacing to 5V logic. Asserted for 100µs
GATE DRIVE
DETECT/
POWER
CC3
V
V
CC3
CC5
. Can be pulled up greater than V
6µA
6µA
V
V
CC3
CC3
CC3
. Can be pulled up greater
V
CC3
6 RST
5
7 SRST
1326 BD
RST
1536fa
CC3