ADM1060ARU-REEL7 Analog Devices Inc, ADM1060ARU-REEL7 Datasheet - Page 43

• Manufacturer Part Number: ADM1060ARU-REEL7
• Description: IC SUPERVISOR/SEQUENCER 28TSSOP
• Manufacturer: Analog Devices Inc
• Type: Sequencerr

Specifications of ADM1060ARU-REEL7

• Rohs Status: RoHS non-compliant
• Number Of Voltages Monitored: 7
• Output: Programmable
• Voltage - Threshold: Adjustable/Selectable
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• For Use With: EVAL-ADM1060EBZ - BOARD EVALUATION ADM1060
• Reset: -
• Reset Timeout: -

SMBus PROTOCOLS FOR RAM AND EEPROM
The ADM1060 contains volatile registers (RAM) and nonvola-
tile EEPROM. User RAM occupies address locations from 0x00
to 0xDF, while EEPROM occupies addresses from 0xF800 to
0xF9FF.
Data can be written to and read from both RAM and EEPROM
as single data bytes.
Data can be written only to unprogrammed EEPROM locations.
To write new data to a programmed location, it is first necessary
to erase it. EEPROM erasure cannot be done at the byte level;
(CONTINUED)
(CONTINUED)
(CONTINUED)
(CONTINUED)
SCL
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
START BY MASTER
START BY MASTER
P
t
BUF
1
S
1
1
1
1
t
D7
HD;STA
1
D7
0
0
D6
D6
t
LOW
1
1
SLAVE ADDRESS
SLAVE ADDRESS
D5
D5
0
FRAME 1
FRAME 1
0
t
D4
HD;DAT
D4
t
DATA BYTE
R
1
FRAME 3
1
DATA BYTE
FRAME 3
D3
D3
A1
A1
Figure 25. General SMBus Write Timing Diagram
Figure 26. General SMBus Read Timing Diagram
D2
D2
A0
A0
Figure 27. Serial Bus Timing Diagram
t
HIGH
D1
D1
R/W
R/W
ACK. BY
ACK. BY
SLAVE
SLAVE
D0
Rev. B | Page 43 of 52
D0
9
ACK. BY
9
MASTER
ACK. BY
SLAVE
t
F
9
9
1
1
D7
t
D7
SU;DAT
D6
D6
the EEPROM is arranged as 16 pages of 32 bytes, and an entire
page must be erased.
Page erasure is enabled by setting Bit 3 in register UPDCFG
(address 0x90) to 1. If this is not set, page erasure cannot occur,
even if the command byte (0xFE) is programmed across the
SMBus.
D5
D5
1
1
D7
D7
S
COMMAND CODE
D4
D4
D6
D6
DATA BYTE
FRAME 2
FRAME 2
t
SU;STA
D3
D3
D5
D5
t
HD;STA
D2
D2
D4
D4
DATA BYTE
FRAME N
DATA BYTE
D1
D1
FRAME N
D3
D3
D0
D0
MASTER
ACK. BY
D2
D2
ACK. BY
SLAVE
9
9
D1
D1
t
SU;STO
D0
D0
ACK. BY
NO ACK.
SLAVE
9
9
ADM1060
P
STOP
BY
MASTER
STOP
BY
MASTER