MAX793SCSE+T Maxim Integrated Products, MAX793SCSE+T Datasheet - Page 16

• Manufacturer Part Number: MAX793SCSE+T
• Description: IC SUPERVISOR MPU 16-SOIC
• Manufacturer: Maxim Integrated Products
• Type: Battery Backup Circuitr

Specifications of MAX793SCSE+T

• Number Of Voltages Monitored: 1
• Output: Open Drain, Push-Pull
• Reset: Active High/Active Low
• Reset Timeout: 140 ms Minimum
• Voltage - Threshold: 2.925V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The power-fail comparator has a typical input hystere-
sis of 10mV. This is sufficient for most applications
where a power-supply line is being monitored through
an external voltage divider (see the section Monitoring
an Additional Power Supply ).
If additional noise margin is desired, connect a resistor
between PFO and PFI as shown in Figure 16a. Select
the ratio of R1 and R2 such that PFI sees V
V
hysteresis and should typically be more than 10 times
the value of R1 or R2. The hysteresis window extends
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
Figure 14. Driving an External Transistor with BATT ON
Figure 15. Using a Super Cap as a Backup Source
16
IN
falls to its trip point (V
______________________________________________________________________________________
(a)
(a)
3.0V OR 3.3V
3.0V OR 3.3V
Adding Hysteresis to the Power-Fail
1N4148
0.47F
Comparator (MAX793/MAX794)
V
BATT
CC
V
CC
TRIP
MAX793
MAX794
MAX793
MAX794
MAX795
GND
BATT ON
). R3 adds the additional
GND
RESET
OUT
OUT
V
CC
PFT
TO STATIC
RAM
TO µP
when
TO CMOS RAM
both above (V
(V
Connecting an ordinary signal diode in series with R3,
as shown in Figure 16b, causes the lower trip point (V
to coincide with the trip point without hysteresis (V
so the entire hysteresis window occurs above V
This method provides additional noise margin without
compromising the accuracy of the power-fail threshold
when the monitored voltage is falling. It is useful for
accurately detecting when a voltage falls past a thresh-
old. The current through R1 and R2 should be at least
1µA to ensure that the 25nA (max over temperature)
PFI input current does not shift the trip point. R3 should
be larger than 82kΩ so it does not load down the PFO
pin. Capacitor C1 is optional, and adds noise rejection.
TRIP
(b)
(b)
+5V
).
1N4148
3.0V OR
0.47F
3.3V
H
) and below (V
V
BATT
CC
V
CC
MAX793
MAX794
MAX793
MAX794
MAX795
D
GND
BATT ON
G
GND
PMOS FET
L
) the original trip point
S
BODY DIODE
RESET
OUT
OUT
V
CC
TO STATIC
RAM
TO µP
TRIP
TRIP
L
),
)
.