LT1763CS8 Linear Technology, LT1763CS8 Datasheet - Page 14
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LT1763CS8
Manufacturer Part Number
LT1763CS8
Description
IC LDO REG LOW NOISE ADJ 8-SOIC
Manufacturer
Linear Technology
Datasheet
1.LT1763CS8PBF.pdf
(22 pages)
Specifications of LT1763CS8
Regulator Topology
Positive Adjustable
Voltage - Output
1.22 ~ 20 V
Voltage - Input
1.8 ~ 20 V
Voltage - Dropout (typical)
0.3V @ 500mA
Number Of Regulators
1
Current - Output
500mA
Current - Limit (min)
520mA
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Voltage Regulator Type
Linear
Topology
LDO
Regulator Output Type
Adjustable
Polarity Type
Positive
Number Of Outputs
Single
Input Voltage (min)
1.8V
Input Voltage (max)
20V
Output Voltage
1.22 to 20V
Package Type
SOIC N
Output Current
500mA
Load Regulation
6mV
Line Regulation
5mV
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Dropout Voltage@current (max)
0.19@10mA/0.22@50mA
Dropout Voltage@current (typ)
0.13@10mA/0.17@50mA
Pin Count
8
Mounting
Surface Mount
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
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PIN FUNCTIONS
LT1763 Series
NC (Pins 1, 4, 9, 12) DE12 Only: No Connect. No connect
pins have no connection to any internal circuitry. These
pins may be tied to either GND or V
OUT (Pins 2, 3/Pin 1): Output. The output supplies power
to the load. A minimum output capacitor of 3.3μF is re-
quired to prevent oscillations. Larger output capacitors
will be required for applications with large transient loads
to limit peak voltage transients. See the Applications Infor-
mation section for more information on output capacitance
and reverse output characteristics.
ADJ (Pin 5/Pin 2): Adjust. For the adjustable LT1763, this
is the input to the error amplifi er. This pin is internally
clamped to ±7V. It has a bias current of 30nA which fl ows
into the pin (see the curve of ADJ Pin Bias Current vs
Temperature in the Typical Performance Characteristics
section). The ADJ pin voltage is 1.22V referenced to ground
and the output voltage range is 1.22V to 20V.
SENSE (Pin 5/Pin 2): Output Sense. For fi xed volt-
age versions of the LT1763 (LT1763-1.5/LT1763-1.8/
LT1763-2.5/LT1763-3/LT1763-3.3/LT1763-5), the SENSE
pin is the input to the error amplifi er. Optimum regula-
tion will be obtained at the point where the SENSE pin
is connected to the OUT pin of the regulator. In critical
applications, small voltage drops are caused by the re-
sistance (R
load. These may be eliminated by connecting the SENSE
pin to the output at the load as shown in Figure 1 (Kelvin
Sense Connection).
Note that the voltage drop across the external PC traces will
add to the dropout voltage of the regulator. The SENSE pin
bias current is 10μA at the nominal rated output voltage. The
SENSE pin can be pulled below ground (as in a dual supply
system where the regulator load is returned to a negative
supply) and still allow the device to start and operate.
14
V
IN
P
+
) of PC traces between the regulator and the
Figure 1. Kelvin Sense Connection
8
5
IN
SHDN
LT1763
GND
(DE12/S8)
3
SENSE
OUT
1
2
R
R
IN
P
P
, or left fl oating.
+
1763 F01
LOAD
BYP (Pin 6/Pin 4): Bypass. The BYP pin is used to bypass
the reference of the LT1763 regulators to achieve low noise
performance from the regulator. The BYP pin is clamped
internally to ±0.6V (one V
output to this pin will bypass the reference to lower the
output voltage noise. A maximum value of 0.01μF can
be used for reducing output voltage noise to a typical
20μV
this pin must be left unconnected.
GND (Pins 7, Exposed Pad Pin 13/Pins 3, 6, 7): Ground.
The exposed pad of the DFN package is an electrical con-
nection to GND. To ensure proper electrical and thermal
performance, solder Pin 13 to the PCB ground and tie
directly to Pin 7. Connect the bottom of the output volt-
age setting resistor divider directly to the GND pins for
optimum load regulation performance.
SHDN (Pin 8/Pin 5): Shutdown. The SHDN pin is used
to put the LT1763 regulators into a low power shutdown
state. The output will be off when the SHDN pin is pulled
low. The SHDN pin can be driven either by 5V logic or
open-collector logic with a pull-up resistor. The pull-up
resistor is required to supply the pull-up current of the
open-collector gate, normally several microamperes, and
the SHDN pin current, typically 1μA. If unused, the SHDN
pin must be connected to V
power shutdown state if the SHDN pin is not connected.
IN (Pin 10, 11/Pin 8): Input. Power is supplied to the device
through the IN pin. A bypass capacitor is required on this
pin if the device is more than six inches away from the
main input fi lter capacitor. In general, the output imped-
ance of a battery rises with frequency, so it is advisable to
include a bypass capacitor in battery-powered circuits. A
bypass capacitor in the range of 1μF to 10μF is suffi cient.
The LT1763 regulators are designed to withstand reverse
voltages on the IN pin with respect to ground and the OUT
pin. In the case of a reverse input, which can happen if
a battery is plugged in backwards, the device will act as
if there is a diode in series with its input. There will be
no reverse current fl ow into the regulator and no reverse
voltage will appear at the load. The device will protect both
itself and the load.
RMS
over a 10Hz to 100kHz bandwidth. If not used,
BE
IN
). A small capacitor from the
. The device will be in the low
1763fg