CS8141YDPSR7 ON Semiconductor, CS8141YDPSR7 Datasheet - Page 4

• Manufacturer Part Number: CS8141YDPSR7
• Description: IC REG LDO LIN 500MA 5V D2PAK-7
• Manufacturer: ON Semiconductor

Specifications of CS8141YDPSR7

• Regulator Topology: Positive Fixed
• Voltage - Output: 5V
• Voltage - Input: 7 ~ 26 V
• Voltage - Dropout (typical): 1.25V @ 500mA
• Number Of Regulators: 1
• Current - Output: 500mA
• Current - Limit (min): 700mA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: TO-263-7, D²Pak (7 leads + Tab), TO-263CA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: CS8141YDPSR7OS

PACKAGE LEAD DESCRIPTION
ELECTRICAL CHARACTERISTICS (continued)
−40°C ≤ T
ENABLE
RESET
Watchdog
4. To observe safe operating junction temperatures, low duty cycle pulse testing is used in tests where applicable.
5. R
6. CS8140 only.
TO−220−7
Threshold
Threshold Hysteresis
Threshold HIGH V
Threshold LOW V
Threshold Hysteresis (V
RESET Output Leakage
Output Voltage Low (V
Output Voltage Low (V
Delay Times t
Delay Times t
Input Voltage High
Input Voltage Low
Input Current
Threshold Frequency f
Threshold Frequency f
HIGH
LOW
RESET = HIGH
(Note 6.)
1
2
3
4
5
6
7
−
−
P
is connected to RESET and V
A
≤ 125°C, unless otherwise noted.) Note 4.
Characteristic
D
POR
WDI(RESET)
2
PACKAGE LEAD #
PAK−7
1
2
3
4
5
6
7
−
−
R(LOW)
R(HI)
L(LOW)
Rpeak
WDI(LOWER)
WDI(UPPER)
RH
13−19, 22
)
SO−24L
1, 6−11,
)
12, 20
)
21
23
24
2
3
4
5
OUT.
5−7, 9, 10
V
V
(HIGH − LOW)
V
V
(HIGH − LOW)
V
1.0 V ≤ V
V
C
C
WDI ≤ V
C
C
DIP−14
OUT
OUT
OUT
OUT
OUT
OUT
DELAY
DELAY
DELAY
DELAY
8, 11
12
13
14
1
2
3
4
, Power up, Power down
≥ 0.5 V, (V
< 0.5 V, (V
Increasing
Decreasing
≥ V
= 0.1 mF
= 0.1 mF
= 0.1 mF
= 0.1 mF
OUT
OUT
R(HI)
(7.0 ≤ V
LEAD SYMBOL
LEAD SYMBOL
≤ V
CS8140, CS8141
Test Conditions
http://onsemi.com
OUT(ON)
OUT(OFF)
R(LOW)
ENABLE
RESET
Sense
Delay
V
GND
WDI
V
NC
OUT
IN
IN
≤ 26 V, 5.0 mA ≤ I
−
−
, R
)
)
P
4
= 2.7 kW, Note 5.
Supply voltage to IC, usually direct from the battery.
CMOS compatible logical input. V
ENABLE is LOW and WDI is beyond its preset limits.
CMOS compatible output lead. RESET goes low whenever
V
2.0 ms or WDI signal falls outside it’s window limits.
Ground Connection.
Timing capacitor for Watchdog and RESET functions.
CMOS compatible input lead. The Watchdog function monitors
the falling edge of the incoming digital pulse train. The signal is
usually generated by the system microprocessor.
Regulated output voltage, 5.0 V (Typ).
No connection.
Kelvin connection which allows remote sensing of output volt-
age for improved regulation.
OUT
drops below 4.5% of it’s typical value for more than
OUT
≤ 500 mA, −40°C ≤ T
4.65
4.50
Min
150
218
3.5
0.5
2.0
30
64
−
−
−
−
−
−
−
FUNCTION
J
4.05
3.95
4.90
4.70
47.5
Typ
100
200
262
OUT
0.1
0.6
1.0
≤ 150°C,
77
−
−
−
0
is disabled when
V
OUT
Max
4.50
4.90
250
326
0.4
1.0
1.5
0.8
25
65
10
96
−
−
−
− 0.05
Unit
mV
mV
ms
ms
mA
mA
Hz
Hz
V
V
V
V
V
V
V
V