CS8140YDWR24 ON Semiconductor, CS8140YDWR24 Datasheet - Page 8

• Manufacturer Part Number: CS8140YDWR24
• Description: IC REG LDO LIN 500MA 5V 24-SOIC
• Manufacturer: ON Semiconductor

Specifications of CS8140YDWR24

• Regulator Topology: Positive Fixed
• Voltage - Output: 5V
• Voltage - Input: 7 ~ 26 V
• Voltage - Dropout (typical): 1.25V @ 500mA
• Number Of Regulators: 1
• Current - Output: 500mA
• Current - Limit (min): 700mA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: CS8140YDWR24OS

circuitry insures that the output current never exceeds a
preset limit.
exceed 180°C (Typ), the power transistor is turned off.
Thermal shutdown is an effective means to prevent die
overheating since the power transistor is the principle heat
source in the IC.
unique combination of control features.
Watchdog and ENABLE Function
Watchdog (Table 1).
Watchdog signal is normal, V
ENABLE is low and the Watchdog signal moves outside
programmable limits, the output transistor turns off and the
IC goes into SLEEP mode. Only the ENABLE circuitry in
the IC remains powered up, drawing a quiescent current of
250 mA.
WDI signal. If the signal falls outside of the WDI window,
a frequency programmable pulse train is generated at the
V
ENABLE
Table 1. V
Should the junction temperature of the power device
The CS8140 differs from all other linear regulators in its
V
As long as ENABLE is high or ENABLE is low and the
The Watchdog monitors the frequency of an incoming
OUT
V
I
OUT
IN
O
H
L
Figure 15. Typical Circuit Waveforms for
is controlled by the logic functions ENABLE and
REGULATOR CONTROL FUNCTIONS
> 30 V
Dump
Load
OUT
Slow
5
0
as a Function of ENABLE and Watchdog
Output Stage Protection
Normal
Circuit
Short
5
5
V
OUT
OUT
(V)
WDI
Fast
5
0
will be at 5.0 V (Typ). If
Shutdown
Thermal
High
5
0
CS8140, CS8141
Low
http://onsemi.com
5
0
8
RESET lead (Figure 16) until the correct Watchdog input
signal reappears at the lead (ENABLE = HIGH).
watchdog function are set by the value of C
are determined according to the following equations for the
CS8140:
equations in (a) above.
the RESET signal and the POWER−ON−RESET (POR)
delay period.
RESET Function
signal is outside of its preset window (Figure 16), when the
regulator is in its power up state (Figure 17) or when V
drops below V
and frequency window, a frequency programmable pulse
train is generated at the RESET lead (Figure 16) until the
correct Watchdog input signal reappears at the lead. The
duration of the RESET pulse is determined by C
according to the following equation:
RESET lead goes low and the delay capacitor, C
discharged. RESET remains low until output is in
regulation, the voltage on C
switching threshold and the Watchdog input signal is within
its set window limits (Figures 17 and 18). The delay after the
output is in regulation is:
external cap C
RESET is operational down to V
and its delay are governed by comparators with hysteresis to
avoid undesirable oscillations.
The lower and upper window threshold limits of the
For the CS8141 the lower limit is determined by the
The capacitor C
The RESET function is activated when the Watchdog
If the Watchdog signal falls outside of the preset voltage
If an undervoltage condition exists, the voltage on the
The RESET delay circuit is also programmed with the
The output of the reset circuit is an open collector NPN.
(b)
(a)
RESET CIRCUIT WAVEFORMS WITH DELAYS
t WDI(LOWER) + (1.3
f WDI(LOWER) + (7.69
t WDI(UPPER) + (3.82
f WDI(UPPER) + (2.62
t WDI(RESET) + (1.0
t POR(typ) + (4.75
DELAY
OUT
DELAY
−4.5% for more than 2.0 ms (Figure 18)
.
INDICATED
also determines the frequency of
DELAY
OUT
10 4) C DELAY
10 5) C DELAY
10 5) C DELAY or
10 −4 )C DELAY or
10 −5 )C DELAY −1
10 −6 )C DELAY −1
= 1.0 V. Both RESET
exceeds the upper
DELAY
. The limits
DELAY
DELAY
OUT
, is