Z8932320VEGR561N Zilog, Z8932320VEGR561N Datasheet - Page 53

• Manufacturer Part Number: Z8932320VEGR561N
• Description: DSP 20MHZ 16BIT W A/D 68PLCC
• Manufacturer: Zilog
• Series: Z893x3r
• Type: Fixed Pointr

Specifications of Z8932320VEGR561N

• Interface: SPI, 3-Wire Serial
• Clock Rate: 20MHz
• Non-volatile Memory: ROM (16 kB)
• On-chip Ram: 1kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4562084

ZiLOG
DS000202-DSP0599
Inst.
Notes:
If src1 is <regind> it must be a bank 1 register. Src2’s <regind> must be a bank 0 register.
<hwregs> for src1 cannot be X.
For the operands <hwregs>, <regind> the <bank switch> defaults to OFF. For the operands <regind>, <regind>
the <bank switch> defaults to ON.
NEG
NOP
OR
POP
PUSH
RET
RL
RR
SCF
SIEF
SLL
SOPF
SRA
SUB
Description
Negate
No operation NOP
Bitwise OR
Pop value
from stack
Push value
onto stack
Return from
subroutine
Rotate Left
Rotate Right RR <cc>,A
Set C flag
Set IE flag
Shift left
logical
Set OP flag
Shift right
arithmetic
Subtract
Synopsis
NEG <cc>,A
OR <dest>,<src>
POP <dest>
PUSH <src>
RET
RL <cc>,A
SCF
SIEF
SLL
SOPF
SRA<cc>,A
SUB<dest>,<src>
Operands
<cc>, A
A
None
A,<pregs>
A,<dregs>
A,<limm>
A,<memind>
A,<direct>
A,<regind>
A,<hwregs>
A,<simm>
<pregs>
<dregs>
<regind>
<hwregs>
<pregs>
<dregs>
<regind>
<hwregs>
<limm>
<accind>
<memind>
None
<cc>,A
A
<cc>,A
A
None
None
[<cc>,]A
A
None
<cc>,A
A
A,<pregs>
A,<dregs>
A,<limm>
A,<memind>
A,<direct>
A,<regind>
A,<hwregs>
A,<simm>
16-Bit Digital Signal Processors with A/D Converter
1
1
1
1
1
2
1
1
1
1
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1
1
2
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1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
Words Cycles Examples
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1
1
1
1
2
3
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1
1
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1
1
1
NEG MI,A
NEG A
OR A,P0:1
OR A, D0:1
OR A,#%2C21
OR A,@@P2:1+
OR A, %2C
OR A,@P1:0–LOOP
OR A,EXT6
OR A,#%12
POP P0:0
POP D0:1
POP @P0:0
POP A
PUSH P0:0
PUSH D0:1
PUSH @P0:0
PUSH BUS
PUSH #12345
PUSH @A
PUSH @@P0:0
RET
RL NZ,A
RL A
RR C,A
RR A
SLL NZ,A
SLL A
SRA NZ,A
SRA A
SUB A,P1:1
SUB A,D0:1
SUB A,#%2C2C
SUB A,@D0:1
SUB A,%15
SUB A,@P2:0–LOOP
SUB A,STACK
SUB A, #%12
NOP
SCF
SIEF
SOPF
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