DSP56311VL150 Freescale Semiconductor, DSP56311VL150 Datasheet - Page 8

• Manufacturer Part Number: DSP56311VL150
• Description: IC DSP 24BIT FIXED POINT 196-BGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of DSP56311VL150

• Interface: Host Interface, SSI, SCI
• Clock Rate: 150MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 384kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.80V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Package: 196MA-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 150 MHz
• Ram Size: 384 KB
• Device Million Instructions Per Second: 150 MIPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Signals/Connections
1.4 PLL
1.5 External Memory Expansion Port (Port A)
Note: When the DSP56311 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-
1.5.1
1-4
CLKOUT
PCAP
PINIT
NMI
A[0–17]
Signal Name
Signal Name
states the relevant Port A signals:
External Address Bus
Output
Input
Input
Input
Output
Type
Type
Chip-driven
Input
Input
Tri-stated
State During
State During
Reset, Stop,
Table 1-6.
Table 1-5.
or Wait
Reset
DSP56311 Technical Data, Rev. 8
A[0–17]
External Address Bus Signals
,
Phase-Locked Loop Signals
Clock Output—Provides an output clock synchronized to the internal core
clock phase.
If the PLL is enabled and both the multiplication and division factors equal one,
then CLKOUT is also synchronized to EXTAL.
If the PLL is disabled, the CLKOUT frequency is half the frequency of EXTAL.
Note: At operating frequencies above 100 MHz, this signal produces a low-
amplitude waveform that is not usable externally by other devices. Above 100
MHz, you can use the asynchronous bus arbitration option that is enabled by
the Asynchronous Bus Arbitration Enable (ABE) bit in the Operating Mode
Register. When set, the DSP enters the Asynchronous Arbitration mode,
which eliminates the BB and BG set-up and hold time requirements with
respect to CLKOUT.
PLL Capacitor—An input connecting an off-chip capacitor to the PLL filter.
Connect one capacitor terminal to PCAP and the other terminal to V
If the PLL is not used, PCAP can be tied to V
PLL Initial—During assertion of RESET, the value of PINIT is written into the
PLL enable (PEN) bit of the PLL control (PCTL) register, determining whether
the PLL is enabled or disabled.
Nonmaskable Interrupt—After RESET deassertion and during normal
instruction processing, this Schmitt-trigger input is the negative-edge-triggered
NMI request internally synchronized to CLKOUT.
D[0–23]
Address Bus—When the DSP is the bus master, A[0–17] are active-high
outputs that specify the address for external program and data memory
accesses. Otherwise, the signals are tri-stated. To minimize power dissipation,
A[0–17] do not change state when external memory spaces are not being
accessed.
,
AA[0
–
3]
,
RD
,
WR
Signal Description
Signal Description
,
BB
.
CC
, GND, or left floating.
Freescale Semiconductor
CCP
.