DSP56321VF200 Freescale Semiconductor, DSP56321VF200 Datasheet

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... By operating in parallel with the core, the EFCOP provides overall enhanced performance and signal quality with no impact on channel throughput or total channel support. This device is pin-compatible with the Freescale DSP56303, DSP56L307, DSP56309, and DSP56311. © Freescale Semiconductor, Inc., 2001, 2005. All rights reserved. Memory Expansion Area Program RAM 32 K × ...

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... Means that a high true (active high) signal is low or that a low true (active low) signal is high Examples: Signal/Symbol PIN PIN PIN PIN Note: Values for , , , and Logic State Signal State True Asserted False Deasserted True Asserted False Deasserted are defined by individual product specifications DSP56321 Technical Data, Rev. 11 pin is active when RESET Voltage Freescale Semiconductor ...

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... Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters (allows six-channel home theater) Internal Peripherals • Serial communications interface (SCI) with baud rate generator • Triple timer module • programmable general-purpose input/output (GPIO) pins, depending on which peripherals are enabled Freescale Semiconductor Table 1. DSP56321 Features Description DSP56321 Technical Data, Rev. 11 iii ...

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... DSP56321 Technical Data, Rev. 11 Instruction MSW2 MSW1 Size* Cache disabled 0 0 enabled 0 0 disabled 0 0 enabled 0 0 disabled 0 1 enabled 0 1 disabled 0 1 enabled 0 1 disabled 1 0 enabled 1 0 disabled 1 0 enabled 1 0 disabled 1 1 enabled 1 1 disabled 1 1 enabled 1 1 Freescale Semiconductor MSW0 ...

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... The documents listed in Table 2 are required for a complete description of the DSP56321 device and are necessary to design properly with the part. Documentation is available from a local Freescale distributor, a Freescale semiconductor sales office Freescale Semiconductor Literature Distribution Center. For documentation updates, visit the Freescale DSP website. See the contact information on the back cover of this document. ...

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... DSP56321 Technical Data, Rev. 11 Freescale Semiconductor ...

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... Chapter 3). There are also two reserved lines. Note: This chapter refers to a number of configuration registers used to select individual multiplexed signal functionality. See the DSP56321 Reference Manual for details on these configuration registers. Freescale Semiconductor DSP56321 Functional Signal Groupings Functional Group DSP56321 Technical Data, Rev. 11 ...

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... SCK0 PC3 SRD0 PC4 STD0 PC5 Port D GPIO 3 PD[0–2] SC1[0–2] SCK1 PD3 SRD1 PD4 STD1 PD5 Port E GPIO PE0 RXD TXD PE1 SCLK PE2 Timer GPIO TIO0 TIO0 TIO1 TIO1 TIO2 TIO2 TCK TDI TDO TMS TRST DE Freescale Semiconductor ...

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... Ground—Connected to an internal device ground plane. Note: The user must provide adequate external decoupling capacitors for all GND connections. 1.3 Clock State During Signal Name Type EXTAL Input Input XTAL Output Chip-driven Freescale Semiconductor Table 1-2. Power Inputs Description . CCQL . CCQL . CCQL . CCQL ...

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... Otherwise tri-stated. Write Enable—When the DSP is the bus master active-low output that is asserted to write external memory on the data bus (D[0–23]). Otherwise, the signals are tri-stated. DSP56321 Technical Data, Rev Signal Description Signal Description Signal Description Freescale Semiconductor ...

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... BG Input Ignored Input BB Input/ Output Ignored Input Freescale Semiconductor External Bus Control Signals (Continued) Signal Description Wait Transfer Acknowledge—If the DSP56321 is the bus master and there is no external bus activity, or the DSP56321 is not the bus master, the TA input is ignored. The TA input is a data transfer acknowledge (DTACK) function that can extend an external bus cycle indefinitely ...

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... MODC, and MODD inputs. The RESET signal must be asserted after powerup. PLL Initial—During assertion of RESET, the value of PINIT determines whether the DPLL is enabled or disabled. Nonmaskable Interrupt—After RESET deassertion and during normal instruction processing, this Schmitt-trigger input is the negative-edge-triggered NMI request. DSP56321 Technical Data, Rev. 11 Signal Description Freescale Semiconductor ...

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... State During Signal Name Type H[0–7] Input/Output HAD[0–7] Input/Output PB[0–7] Input or Output Freescale Semiconductor Host Port Usage Considerations Description Table 1-10. Host Interface 1,2 Reset Ignored Input Host Data—When the HI08 is programmed to interface with a non-multiplexed host bus and the HI function is selected, these signals are lines 0–7 of the bidirectional Data bus. Host Address— ...

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... Schmitt-trigger input. The polarity of the data strobe is programmable but is configured as active-low (HRD) after reset. Port B 11—When the HI08 is configured as GPIO through the HI08 Port Control Register, this signal is individually programmed as an input or output through the HI08 Data Direction Register. DSP56321 Technical Data, Rev. 11 Signal Description Freescale Semiconductor ...

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... If the last state is input, the signal is an ignored input. • If the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-stated. 2. The Wait processing state does not affect the signal state. Freescale Semiconductor Table 1-10. Host Interface (Continued) 1,2 ...

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... Port C 4—The default configuration following reset is GPIO input PC4. When configured as PC4, signal direction is controlled through the Port C Direction Register. The signal can be configured as an ESSI signal SRD0 through the Port C Control Register. DSP56321 Technical Data, Rev. 11 Signal Description Freescale Semiconductor ...

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... Input/Output PD1 Input or Output SC12 Input/Output PD2 Input or Output Freescale Semiconductor Enhanced Synchronous Serial Interface 1 (ESSI1) Enhanced Synchronous Serial Interface 0 (Continued) 1,2 Reset Ignored Input Serial Transmit Data—Transmits data from the Serial Transmit Shift Register. STD0 is an output when data is transmitted. ...

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... Port E 1—The default configuration following reset is GPIO input PE1. When configured as PE1, signal direction is controlled through the Port E Direction Register. The signal can be configured as an SCI signal TXD through the Port E Control Register. DSP56321 Technical Data, Rev. 11 Signal Description Signal Description Freescale Semiconductor ...

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... If the last state is input, the signal is an ignored input. • If the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-stated. 2. The Wait processing state does not affect the signal state. Freescale Semiconductor Serial Communication Interface (Continued) 1,2 Reset Ignored Input Serial Clock— ...

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... OnCE module to initiate debug mode directly or to provide a direct external indication that the chip has entered Debug mode. All other interface with the OnCE module must occur through the JTAG port. DSP56321 Technical Data, Rev. 11 Signal Description Freescale Semiconductor ...

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... Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent damage to the device. 3. Power-up sequence: During power-up, and throughout the DSP56321 operation, V equal to V voltage. CCQL Freescale Semiconductor CAUTION Table 2-1. Absolute Maximum Ratings Symbol V CCQL ...

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... CCQH –0.3 — 0.8 –0.3 — 0.8 0.2 × V –0.3 — CCQH –10 — 10 –10 — 10 2.4 — — – 0.01 — — — — 0.4 — — 0.01 Freescale Semiconductor Unit C/W C/W C/W C/W C/W C/W Unit µA µ ...

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... With DPLL disabled • With DPLL enabled Internal clock cycle time • With DPLL disabled • With DPLL enabled Internal clock high period • With DPLL disabled • With DPLL enabled Freescale Semiconductor Table 2-3. DC Electrical Characteristics Symbol I CCI I CCW I CCS 1.6 V ± 0 – ...

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... MHz 275 MHz Max Min Max Min 0 MHz 240 MHz 0 MHz 275 MHz 16 MHz 240 MHz 16 MHz 275 MHz ∞ ∞ 1.95 ns 1.70 ns 1.77 ns 35.9 ns 1.55 ns ∞ ∞ 1.95 ns 1.70 ns 1.77 ns 35.9 ns 1.55 ns Freescale Semiconductor C Max ∞ 35.9 ns ∞ 35.9 ns ...

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... Predivider output clock frequency range 2 Total multiplication factor Multiplication factor integer part 3 Multiplication factor numerator Multiplication factor denominator Double clock frequency range DDFR 4 Phase lock-in time Freescale Semiconductor External Clock Operation (Continued) 200 MHz 220 MHz Min Max Min C ∞ 5 ...

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... Note 7 — Note 7 — Note 7 ns Freescale Semiconductor ...

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... Data write to HI08, ESSI, SCI • Timer • IRQ, NMI (edge trigger) 29 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external memory (DMA source) access address out valid Freescale Semiconductor 200 MHz Expression Min Max (WS + 3.25) × T – — Note 7 C 10.94 ( × ...

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... pF Reset Value Figure 2-3. Reset Timing DSP56321 Technical Data, Rev (CONTINUED) 220 MHz 240 MHz 275 MHz Max Min Max Min Max is valid, and the EXTAL input valid. The specified timing reflects First Fetch Freescale Semiconductor Unit ...

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... IRQC, IRQD, NMI General Purpose I/O IRQA, IRQB, IRQC, IRQD, NMI IRQA, IRQB, IRQC, IRQD, NMI IRQA, IRQB, IRQC, IRQD, NMI Figure 2-5. Freescale Semiconductor First Interrupt Instruction Execution/Fetch First Interrupt Instruction Execution 18 b) General-Purpose I/O Figure 2-4. External Fast Interrupt Timing 15 ...

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... Recovery from Stop State Using IRQA Interrupt Service DMA Source Address 29 First Interrupt Instruction Execution External Memory Access (DMA Source) Timing DSP56321 Technical Data, Rev IRQA, IRQB, IRQC, IRQD, NMI V IL First Instruction Fetch First IRQA Interrupt Instruction Fetch Freescale Semiconductor ...

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... WR deassertion to data — high impedance 112 Previous RD deassertion — to data active (write) 113 RD deassertion time — 4 114 WR deassertion time — Freescale Semiconductor Table 2-8. SRAM Timing 200 MHz 220 MHz 1 Expression Min Max Min ( × T − 4.0 21.0 18 ...

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... Min Max Min Max 0.3 — 0.1 — –0.18 — — 10.55 — 8.81 — — 1.21 — 0.54 — — 5.38 — 4.18 — — 3.04 — 2.91 — 0 — 0 — 0 — 117 106 118 119 Data In Freescale Semiconductor Unit ...

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... To guarantee timings 250 and 251 recommended that you assert non-overlapping BG inputs to different DSP56300 devices (on the same bus), as shown in Figure 2-12, where BG1 is the BG signal for one DSP56300 device while BG2 is the BG signal for a second DSP56300 device. Freescale Semiconductor 100 107 101 ...

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... Freescale Semiconductor BG Uni ...

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... Data Register” read or write (HROD=0) 341 Delay from data strobe assertion to host request deassertion for “Last Data Register” read or write (HROD=1, open drain host request) Freescale Semiconductor 1,2,12 Host Interface Timings (Continued) 200 MHz 220 MHz Expression Min ...

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... Max = 1.6 V ± 0 –40°C to +100 ° 317 327 326 Host Interrupt Vector Register (IVR) Read Timing Diagram DSP56321 Technical Data, Rev. 11 (Continued) 220 MHz 240 MHz 275 MHz Min Max Min Max Min Max = 318 328 329 Freescale Semiconductor Uni t ...

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... HRRQ (double host request) Figure 2-14. Read Timing Diagram, Non-Multiplexed Bus, Single Data Strobe HREQ (single host request) HRRQ (double host request) Figure 2-15. Read Timing Diagram, Non-Multiplexed Bus, Double Data Strobe Freescale Semiconductor HA[2–0] 336 337 330 HCS 336 ...

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... HCS 336 HRW 320 HDS 324 H[7–0] 340 341 HA[2–0] 336 337 331 HCS 320 HWR 324 H[7–0] 340 341 DSP56321 Technical Data, Rev. 11 333 337 321 325 339 333 321 325 339 Freescale Semiconductor ...

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... HREQ (single host request) HRRQ (double host request) Figure 2-18. HREQ (single host request) HRRQ (double host request) Figure 2-19. Read Timing Diagram, Multiplexed Bus, Double Data Strobe Freescale Semiconductor , HA[10–8] 336 322 HAS 323 336 HRW 317 HDS 334 ...

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... Address Data 340 341 Write Timing Diagram, Multiplexed Bus, Single Data Strobe , 336 322 HAS 323 320 HWR 334 324 335 Data Address 340 341 DSP56321 Technical Data, Rev. 11 337 337 321 325 339 337 321 325 339 Freescale Semiconductor ...

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... In the timing diagrams that follow, the SCLK is drawn using the clock falling edge as a the first reference. Clock polarity is programmable in the SCI Control Register (SCR). Refer to the DSP56321 Reference Manual for details. Freescale Semiconductor Table 2-11. SCI Timings 200 MHz ...

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... Data Valid 405 406 Data Valid a) Internal Clock 400 402 401 407 408 Data Valid 409 410 Data Valid b) External Clock SCI Synchronous Mode Timing 411 412 413 414 415 Data Valid SCI Asynchronous Mode Timing DSP56321 Technical Data, Rev. 11 Freescale Semiconductor ...

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... TXC rising edge to FST out (word- 2 length-relative) low 450 TXC rising edge to FST out (word- length) high Freescale Semiconductor Table 2-12. ESSI Timings 200 MHz 220 MHz Symbol Expression Min Max Min Max Min Max Min Max 6 × ...

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... Freescale Semiconductor Unit ...

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... FST (Bit) In FST (Word) In Flags Out Note: In Network mode, output flag transitions can occur at the start of each time slot within the frame. In Normal mode, the output flag state is asserted for the entire frame period. Freescale Semiconductor 430 432 446 447 450 454 ...

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... DSP56321 Technical Data, Rev. 11 438 440 Last Bit 443 445 220 MHz 240 MHz 240 MHz 11.1 — 10.3 — 9.27 — 11.1 — 10.3 — 9.27 — 56.6 — 52.7 — 47.2 — Freescale Semiconductor Unit ...

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... The read operation occurs during a simultaneous change of GPIO pins (for example, the change may happen through an intermediate state 10). Therefore, when GPIO bits are read, the recommended practice is to poll continuously until two consecutive read operations have identical results. Freescale Semiconductor 480 481 TIO Timer Event Input Restrictions ...

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... DSP56321 Technical Data, Rev. 11 All frequencies Min Max 0.0 22.0 45.0 — 20.0 — 0.0 3.0 5.0 — 24.0 — 0.0 40.0 0.0 40.0 5.0 — 25.0 — 0.0 44.0 0.0 44.0 100.0 — 40.0 — pF. 502 V M 503 Freescale Semiconductor Unit MHz ...

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... TDO (Output) TDO (Output) TDO (Output) Figure 2-30. TCK (Input) TRST (Input) Freescale Semiconductor 504 Input Data Valid 506 Output Data Valid 507 506 Output Data Valid Boundary Scan (JTAG) Timing Diagram 508 Input Data Valid 510 Output Data Valid ...

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... Max 22.0 MHz 1.5 × T 5.5 × × –40°C to +100 ° 514 515 Figure 2-32. OnCE—Debug Request DSP56321 Technical Data, Rev. 11 All Frequencies Unit Min Max 0.0 22.0 MHz + 10.0 20.0 — 30.0 — 67 5.0 + 25.0 — 516 Freescale Semiconductor ...

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... Packaging This section includes diagrams of the DSP56321 package pin-outs and tables showing how the signals described in Chapter 1 are allocated for the package. The DSP56321 is available in a 196-pin molded array plastic-ball grid array (MAP-BGA) package. Freescale Semiconductor DSP56321 Technical Data, Rev 3-1 ...

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... D13 D10 D12 CCD GND GND CCD GND GND A17 A16 D0 GND GND V A14 A15 CCQH GND GND A13 V A12 CCQL GND GND V A10 A11 CCA GND GND GND GND CCA GND GND CCA Res’d V AA0 A0 CCC AA1 NC Freescale Semiconductor ...

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... A11 A10 V GND CCA GND GND CCA GND CCA AA0 V CCC AA1 Figure 3-2. Freescale Semiconductor Bottom View D14 D16 D19 V D23 CCD D13 D15 D17 D20 D21 D12 V D18 V D22 CCD CCQL GND GND GND GND GND GND GND GND ...

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... GND D10 GND D11 GND D12 D1 D13 D2 D14 V CCD E1 STD0 or PC5 E2 V CCS E3 SRD0 or PC4 E4 GND E5 GND E6 GND E7 GND E8 GND E9 GND E10 GND E11 GND E12 A17 E13 A16 E14 D0 F1 RXD or PE0 F2 SC10 or PD0 F3 SC00 or PC0 F4 GND F5 GND Freescale Semiconductor ...

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... G7 GND G8 GND G9 GND G10 GND G11 GND G12 A13 G13 V CCQL G14 A12 H1 V CCQH H2 V CCQL Freescale Semiconductor Signal List by Ball Number (Continued) Ball Signal Name No. H3 SCK0 or PC3 H4 GND H5 GND H6 GND H7 GND H8 GND H9 GND H10 GND H11 GND H12 ...

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... RESET N6 GND N7 AA3 CCQL N10 Reserved N11 BR N12 V CCC N13 AA0 N14 A0 DSP56321 Technical Data, Rev. 11 Ball Signal Name No H5, HAD5, or PB5 P3 H3, HAD3, or PB3 P4 H1, HAD1, or PB1 GND P7 AA2 P8 XTAL P9 V CCC P10 TA P11 BB P12 AA1 P13 BG P14 NC Freescale Semiconductor ...

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... L14 A5 K13 A6 K14 A7 J13 A8 J12 A9 J14 AA0 N13 AA1 P12 AA2 P7 AA3 N7 BB P11 BG P13 Freescale Semiconductor Table 3-2. Signal List by Signal Name Ball Signal Name No. BR N11 D0 E14 D1 D12 D10 B11 D11 A11 D12 C10 D13 B10 D14 A10 D15 ...

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... GND L11 GND N6 GND HA0 M3 DSP56321 Technical Data, Rev. 11 Ball Signal Name No. HA1 M1 HA10 L1 HA2 M2 HA8 M1 HA9 M2 HACK/HACK J1 HAD0 M5 HAD1 P4 HAD2 N4 HAD3 P3 HAD4 N3 HAD5 P2 HAD6 N1 HAD7 N2 HAS/HAS M3 HCS/HCS L1 HDS/HDS J3 HRD/HRD J2 HREQ/HREQ K2 HRRQ/HRRQ J1 HRW J2 HTRQ/HTRQ K2 HWR/HWR J3 IRQA C4 IRQB A5 IRQC C5 IRQD B5 Freescale Semiconductor ...

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... A14 NC B14 NC M10 P14 NMI D1 PB0 M5 PB1 P4 PB10 M2 PB11 J2 PB12 J3 PB13 L1 PB14 K2 PB15 J1 PB2 N4 PB3 P3 Freescale Semiconductor Signal List by Signal Name (Continued) Ball Signal Name No. PB4 N3 PB5 P2 PB6 N1 PB7 N2 PB8 M3 PB9 M1 PC0 F3 PC1 D2 PC2 C1 PC3 H3 PC4 E3 PC5 E1 PD0 F2 PD1 A2 PD2 B2 PD3 ...

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... CCC V A7 CCD V C9 CCD V C11 CCD V D14 CCD V M4 CCH V F12 CCQH V H1 CCQH V M7 CCQH DSP56321 Technical Data, Rev. 11 Ball Signal Name No CCQL V G13 CCQL V H2 CCQL V M6 CCQL V N9 CCQL V E2 CCS V K1 CCS WR M11 XTAL P8 Freescale Semiconductor ...

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... To minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. Freescale Semiconductor , in ° C can be obtained from this equation: J × ...

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... V CCQL (I/O) power connections positioned as closely as possible to the four sides of . GND and V CC DSP56321 Technical Data, Rev )/P . This value gives a better estimate pin on the DSP and from the V CC and V GND CC . GND , , IRQA IRQB IRQC Freescale Semiconductor pins , , IRQD ...

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... C V Where For a Port A address pin loaded with 50 pF capacitance, operating at 3.3 V, with a 66 MHz clock, toggling at its maximum possible rate (33 MHz), the current consumption is expressed in Equation 4. Freescale Semiconductor and circuits. GND , , ). TMS the V RESET duration” conditions are met (see Table 2-7), the device ...

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... F2 F1 – typF2 typF1 current at F2 current at F1 high frequency (any specified operating frequency) low frequency (any specified operating frequency lower than F2) is 0.5 percent. If the rate of change of the frequency of EXTAL DSP56321 Technical Data, Rev value CCItyp is slow EXTAL Freescale Semiconductor ...

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... PLOAD_LOOP ; ; Load the X-data ; move #INT_XDAT,r0 move #XDAT_START,r1 do #(XDAT_END-XDAT_START),XLOAD_LOOP move p:(r1)+,x0 move x0,x:(r0)+ XLOAD_LOOP Freescale Semiconductor Typical Power Consumption ; BCR: Area w.s (SRAM) ; XTAL disable ; PLL enable DSP56321 Technical Data, Rev A-1 ...

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... PROG_END nop nop XDAT_START ; org x:0 dc $262EB9 dc $86F2FE dc $E56A5F dc $616CAC dc $8FFD75 dc $9210A dc $A06D7B dc $CEA798 dc $8DFBF1 dc $A063D6 dc $6C6657 dc $C2A544 dc $A3662D dc $A4E762 dc $84F0F3 dc $E6F1B0 A-2 ; ebd y:(r4)+,y1 y:(r4)+,y0 y:(r4)+,y0 DSP56321 Technical Data, Rev. 11 Freescale Semiconductor ...

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... XDAT_END YDAT_START ; org y:0 dc $5B6DA dc $C3F70B dc $6A39E8 dc $81E801 dc $C666A6 dc $46F8E7 dc $AAEC94 dc $24233D dc $802732 dc $2E3C83 dc $A43E00 Freescale Semiconductor DSP56321 Technical Data, Rev. 11 A-3 ...

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... YDAT_END ;************************************************************************** ; ; EQUATES for DSP56321 I/O registers and ports ; ;************************************************************************** page 132,55,0,0,0 opt mex A-4 DSP56321 Technical Data, Rev. 11 Freescale Semiconductor ...

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... M_HGEN EQU $0 M_HA8EN EQU $1 M_HA9EN EQU $2 M_HCSEN EQU $3 M_HREN EQU $4 M_HAEN EQU $5 M_HEN EQU $6 Freescale Semiconductor ; Host port GPIO data Register ; Host port GPIO direction Register ; Port C Control Register ; Port C Direction Register ; Port C GPIO Data Register ; Port D Control register ; Port D Direction Data Register ...

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... Timer Interrupt Rate ; SCI Clock Polarity ; SCI Error Interrupt Enable (REIE) ; Transmitter Empty ; Transmit Data Register Empty ; Receive Data Register Full ; Idle Line Flag ; Overrun Error Flag ; Parity Error ; Framing Error Flag ; Received Bit 8 (R8) Address DSP56321 Technical Data, Rev. 11 Freescale Semiconductor ...

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... M_SCD0 EQU 2 M_SCD1 EQU 3 M_SCD2 EQU 4 M_SCKD EQU 5 M_SHFD EQU 6 M_FSL EQU $180 M_FSL0 EQU 7 Freescale Semiconductor ; Clock Divider Mask (CD0-CD11) ; Clock Out Divider ; Clock Prescaler ; Receive Clock Mode Source Bit ; Transmit Clock Source Bit ; SSI0 Transmit Data Register 0 ; SSIO Transmit Data Register 1 ...

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... SSI Transmit Slot Bits Mask A (TS0-TS15) ; SSI Transmit Slot Bits Mask B (TS16-TS31) ; SSI Receive Slot Bits Mask A (RS0-RS15) ; SSI Receive Slot Bits Mask B (RS16-RS31) ; Interrupt Priority Register Core ; Interrupt Priority Register Peripheral ; IRQA Mode Mask DSP56321 Technical Data, Rev. 11 Freescale Semiconductor ...

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... EQUATES for TIMER ; ;------------------------------------------------------------------------ ; Register Addresses Of TIMER0 M_TCSR0 EQU $FFFF8F Freescale Semiconductor ; IRQA Mode Interrupt Priority Level (low) ; IRQA Mode Interrupt Priority Level (high) ; IRQA Mode Trigger Mode ; IRQB Mode Mask ; IRQB Mode Interrupt Priority Level (low) ; IRQB Mode Interrupt Priority Level (high) ...

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... Prescaled Clock Enable ; Timer Overflow Flag ; Timer Compare Flag ; Prescaler Source Mask ; Timer Control 0 ; Timer Control 1 ; Timer Control 2 ; Timer Control 3 ; DMA Status Register ; DMA Offset Register 0 ; DMA Offset Register 1 ; DMA Offset Register 2 ; DMA Offset Register 3 DSP56321 Technical Data, Rev. 11 Freescale Semiconductor ...

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... M_DAM4 EQU 8 M_DAM5 EQU 9 M_D3D EQU 10 M_DRS EQU $F800 M_DCON EQU 16 M_DPR EQU $60000 Freescale Semiconductor ; DMA0 Source Address Register ; DMA0 Destination Address Register ; DMA0 Counter ; DMA0 Control Register ; DMA1 Source Address Register ; DMA1 Destination Address Register ; DMA1 Counter ; DMA1 Control Register ...

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... EFCOP Coefficient Base Address ; EFCOP Decimation/Channel Register ; PLL Control Register ; Multiplication Factor Intager Bits Mask (MFI0-MFI3) ; Multiplication Factor Bits Mask (MFN0-MFN6) ; Multiplication Factor Bits Mask (MFD0-MFD6) ; PreDivider Factor Bits Mask (PD0-PD3 Division Factor Bits Mask (DF0-DF2) DSP56321 Technical Data, Rev. 11 Freescale Semiconductor ...

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... M_BNC EQU $F00 M_BAC EQU $FFF000 ; control and status bits in SR M_CP EQU $c00000 M_CA EQU 0 M_V EQU 1 Freescale Semiconductor ; PLL Clock Output Disable Bit ; STOP Processing State Bit ; XTAL Disable Bit ; PLL Enable Bit ; Bus Control Register ; DRAM Control Register ...

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... Bus Release Timing ; Address Tracing Enable bit in OMR. ; Stack Extension space select bit in OMR. ; Extensed stack UNderflow flag in OMR. ; Extended stack OVerflow flag in OMR. ; Extended WRaP flag in OMR. ; Stack Extension Enable bit in OMR. ;leave user definition as is. DSP56321 Technical Data, Rev. 11 Freescale Semiconductor ...

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... I_SI1TDE EQU I_VEC+$48 I_SI1TLS EQU I_VEC+$4A ;------------------------------------------------------------------------ ; SCI Interrupts ;------------------------------------------------------------------------ I_SCIRD EQU I_VEC+$50 I_SCIRDE EQU I_VEC+$52 I_SCITD EQU I_VEC+$54 I_SCIIL EQU I_VEC+$56 I_SCITM EQU I_VEC+$58 Freescale Semiconductor ; Hardware RESET ; Stack Error ; Illegal Instruction ; Debug Request ; Trap ; Non Maskable Interrupt ; IRQA ; IRQB ; IRQC ; IRQD ...

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... I_VEC+$68 I_FDOIE EQU I_VEC+$6A ;------------------------------------------------------------------------ ; INTERRUPT ENDING ADDRESS ;------------------------------------------------------------------------ I_INTEND EQU I_VEC+$FF A-16 ; Host Receive Data Full ; Host Transmit Data Empty ; Default Host Command ; EFilter input buffer empty ; EFilter output buffer full ; last address of interrupt vector space DSP56321 Technical Data, Rev. 11 Freescale Semiconductor ...

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... Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2001, 2005. Order Number DSP56321VL200 DSP56321VF200 DSP56321VL220 DSP56321VF220 DSP56321VL240 DSP56321VF240 DSP56321VL275 ...