MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 7

• Manufacturer Part Number: MCF5272CVF66
• Description: IC MPU 32BIT 66MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Not Compliant

1.2.5
For system diagnostics and manufacturing testing, the MCF5272 includes user-accessible test logic that
complies with the IEEE 1149.1 standard for boundary scan testing, often referred to as JTAG (Joint Test
Action Group). The IEEE 1149.1 Standard provides more information.
1.3
This section presents issues to consider when designing with the MCF5272. It describes differences
between the MCF5272 (core and peripherals) and various other standard components that are replaced by
moving to an integrated device like the MCF5272.
1.3.1
The MCF5272 has flexibility in its system bus interfacing due to the dynamic bus sizing feature in which
32-,16-, and 8-bit data bus sizes are programmable on a per-chip select basis. The programmable nature of
the strobe signals (including OE/RD, R/W, BS[3:0], and CSn) should ensure that external decode logic is
minimal or nonexistent. Configuration software is required upon power-on reset before chip-selected
devices can be used, except for chip select 0 (CS0), which is active after power-on reset until programmed
otherwise. BUSW1 and BUSW0 select the initial data bus width for CS0 only. A wake-up from sleep mode
or a restart from stop mode does not require reconfiguration of the chip select registers or other system
configuration registers.
1.4
This section describes features peculiar to the MCF5272.
1.4.1
The physical layer interface controller (PLIC) allows the MCF5272 to connect at a physical level with
external CODECs and other peripheral devices that use either the general circuit interface (GCI), or
interchip digital link (IDL), physical layer protocols. This module is primarily intended to facilitate designs
that include ISDN interfaces.
1.4.2
The PWM unit is intended for use in control applications. With a suitable low-pass filter, it can be used as
a digital-to-analog converter. This module generates a synchronous series of pulses. The duty cycle of the
pulses is under software control.
Its main features include the following:
The PWM implements a simple free-running counter with a width register and comparator such that the
output is cleared when the counter exceeds the value of the width register. When the counter wraps around,
MOTOROLA
•
•
•
•
Double-buffered width register
Variable-divide prescale
Three identical, independent PWM modules
Byte-wide width register provides programmable control of duty cycle.
MCF5272-Specific Features
System Design
Test Access Port
System Bus Configuration
Physical Layer Interface Controller (PLIC)
Pulse-Width Modulation (PWM) Unit
MCF5272 Integrated Microprocessor Product Brief
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
System Design
7