MCF5272VF66 Freescale Semiconductor, MCF5272VF66 Datasheet - Page 5
![IC MPU 32BIT 66MHZ 196-MAPBGA](/photos/13/94/139412/mcf5272vf66_sml.jpg)
MCF5272VF66
Manufacturer Part Number
MCF5272VF66
Description
IC MPU 32BIT 66MHZ 196-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272VF66
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
196-MAPBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272VF66
Manufacturer:
HYNIX
Quantity:
19
Company:
Part Number:
MCF5272VF66
Manufacturer:
FREESCAL
Quantity:
885
Company:
Part Number:
MCF5272VF66
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MCF5272VF66
Manufacturer:
FREESCALE
Quantity:
20 000
Company:
Part Number:
MCF5272VF66J
Manufacturer:
Freescale
Quantity:
256
Company:
Part Number:
MCF5272VF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MCF5272VF66R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MCF5272VF66R2J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
decrement and branch, integer division, and integer multiply with a 64-bit result. Also, four indirect
addressing modes have been eliminated.
The ColdFire 2 core incorporates a complete debug module that provides real-time trace, background debug
mode, and real-time debug support.
1.2.2
The MCF5272 SIM provides the external bus interface for the ColdFire 2 architecture. It also eliminates
most or all of the glue logic that typically supports the microprocessor and its interface with the peripheral
and memory system. The SIM provides programmable circuits to perform address-decoding and chip
selects, wait-state insertion, interrupt handling, clock generation, discrete I/O, and power management
features.
1.2.2.1
The external bus interface (EBI) handles the transfer of information between the internal core and memory,
peripherals, or other processing elements in the external address space.
1.2.2.2
Programmable chip select outputs provide signals to enable external memory and peripheral circuits,
providing all handshaking and timing signals for automatic wait-state insertion and data bus sizing.
Base memory address and block size are programmable, with some restrictions. For example, the starting
address must be on a boundary that is a multiple of the block size. Each chip select is general purpose;
however, any one of the chip selects can be programmed to provide read and write enable signals suitable
for use with most popular static RAMs and peripherals. Data bus width (8-bit, 16-bit, or 32-bit) is
programmable on all chip selects, and further decoding is available for protection from user mode access or
read-only access.
1.2.2.3
The SIM provides configuration registers that allow general system functions to be controlled and
monitored. For example, all on-chip registers can be relocated as a block by programming a module base
address, power management modes can be selected, and the source of the most recent RESET or BERR can
be checked. The hardware watchdog features can be enabled or disabled, and the bus time-out period can
be programmed.
A software watchdog timer is also provided for system protection. If programmed, the timer causes a reset
to the MCF5272 if it is not refreshed periodically by software.
1.2.2.4
The sleep and stop power management modes reduce power consumption by allowing software to shut
down the core, peripherals, or the whole device during inactive periods. To reduce power consumption
further, software can individually disable internal clocks to the on-chip peripheral modules. The
power-saving modes are described as follows:
MOTOROLA
•
Sleep mode uses interrupt control logic to allow any interrupt condition to wake the processor. As
the MCF5272 is fully static, sleep mode is simply the disabling of the core’s clock after the current
instruction completes. An interrupt from any internal or external source causes on-chip power
System Integration Module (SIM)
External Bus Interface
Chip Select and Wait State Generation
System Configuration and Protection
Power Management
MCF5272 Integrated Microprocessor Product Brief
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
MCF5272 Architecture
5