MCF5282CVF80 Freescale Semiconductor, MCF5282CVF80 Datasheet - Page 577

• Manufacturer Part Number: MCF5282CVF80
• Description: IC MPU 32BIT 66MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Digital Ic Case Style: MAPBGA
• Rohs Compliant: No
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF528x
• Maximum Speed: 80 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 150
• Interface Type: CAN/Ethernet/I2C/QSPI/UART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 12
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

The next two situations consider trigger events that occur for the lower priority queue 2, while queue 1 is
actively being serviced.
Situation S4
saved, and as soon as queue 1 is finished, queue 2 servicing begins.
Situation S5
busy, the trigger overrun error bit is set, but queue 1 execution is not disturbed. Situation S5 also shows
that the effect of queue 2 trigger events during queue 1 execution is the same when the pause feature is
used for either queue.
Freescale Semiconductor
Q1:
Q2:
QS:
Q1:
Q2:
QS:
(Figure
(Figure
0000
IDLE
Q1:
IDLE
T1
28-27) shows that when multiple queue 2 trigger events are detected while queue 1 is
28-26) shows that a queue 2 trigger event is recognized while queue 1 is active is
0000
C1
IDLE
TOR1
ACTIVE
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
T1
1000
IDLE
C2
Q1:
PF1
T1
Figure 28-25. CCW Priority Situation 3
Figure 28-26. CCW Priority Situation 4
0100
C1
Q2:
1000
T2
C2
Q2:
PAUSE
ACTIVE
C1
TOR2
ACTIVE
T2
T2
0110
TRIGGERED
C3
C2
1011
PF2
C4
0101
CF1
T1
C1
C3
TOR1
ACTIVE
T1
1001
PAUSE
C2
C4
ACTIVE
0010
CF1
C3
0001
C4
Queued Analog-to-Digital Converter (QADC)
CF2
T2
IDLE
C3
TOR2
ACTIVE
T2
0010
IDLE
C4
CF2
IDLE
0000
IDLE
0000
28-39