SP3243EET-L Exar Corporation, SP3243EET-L Datasheet - Page 10

• Manufacturer Part Number: SP3243EET-L
• Description: IC TXRX RS232 INTELLIGNT 28WSOIC
• Manufacturer: Exar Corporation
• Type: Transceiverr

Specifications of SP3243EET-L

• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• Number Of Drivers/receivers: 3/5
• Protocol: RS232
• Voltage - Supply: 3 V ~ 5.5 V
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Function: Transceiver
• Mounting Style: SMD/SMT
• Supply Current: 1 uA
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 3 V
• Logic Type: RS-232 Transceivers
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1122-5

truth table logic of the SP3243 driver and receiver
outputs can be found in Table 2.
The SP3243 includes an additional non-invert-
ing receiver with an output R
extra output that remains active and
monitors activity while the other receiver
outputs are forced into high impedance.
This allows Ring Indicator (RI) from a
peripheral to be monitored without forward
biasing the TTL/CMOS inputs of the other
devices connected to the receiver outputs.
Since receiver input is usually from a transmis-
sion line where long cable lengths and system
interference can degrade the signal, the inputs
have a typical hysteresis margin of 300mV. This
ensures that the receiver is virtually immune to
noisy transmission lines. Should an input be left
unconnected, an internal 5KΩ pulldown resistor
to ground will commit the output of the receiver
to a HIGH state.
Charge Pump
The charge pump is a Sipex–patented design
(U.S. 5,306,954) and uses a unique approach
compared to older less–efficient designs. The
charge pump still requires four external
capacitors, but uses a four–phase voltage
shifting technique to attain symmetrical 5.5V
power supplies. The internal power supply con-
sists of a regulated dual charge pump that pro-
vides output voltages 5.5V regardless of the
input voltage (V
range. This is important to maintain compliant
RS-232 levels regardless of power supply
fluctuations.
The charge pump operates in a discontinuous
mode using an internal oscillator. If the output
voltages are less than a magnitude of 5.5V, the
charge pump is enabled. If the output voltages
exceed a magnitude of 5.5V, the charge pump is
disabled. This oscillator controls the four phases
of the voltage shifting. A description of each
phase follows.
Phase 1
Date: 2/05/06
CC
) over the +3.0V to +5.5V
2
OUT. R
SP3243 +3.0V to +5.5V RS-232 Transceivers
2
OUT is an
10
— V
the clock cycle, the positive side of capacitors
C
then switched to GND and the charge in C
transferred to C
V
now 2 times V
Phase 2
— V
connects the negative terminal of C
storage capacitor and the positive terminal of C
to GND. This transfers a negative generated
voltage to C 4 . This generated voltage is
regulated to a minimum voltage of -5.5V.
Simultaneous with the transfer of the voltage to
C
to V
GND.
Phase 3
— V
clock is identical to the first phase — the charge
transferred in C
terminal of C
side of capacitor C
voltage potential across C
Phase 4
— V
connects the negative terminal of C
and transfers this positive generated voltage
across C
voltage is regulated to +5.5V. At this voltage,
the internal oscillator is disabled. Simultaneous
with the transfer of the voltage to C
positive side of capacitor C
and the negative side is connected to GND,
allowing the charge pump cycle to begin again.
The charge pump cycle will continue as long as
the operational conditions for the internal
oscillator are present.
Since both V
from V
be symmetrical. Older charge pump approaches
that generate V
the magnitude of V
inherent inefficiencies in the design. The clock
rate for the charge pump typically operates at
greater than 250kHz. The external capacitors
can be as low as 0.1μF with a 16V breakdown
voltage rating.
1
4
CC
, the positive side of capacitor C
and C
, the voltage potential across capacitor C
DD
CC
DD
SS
SS
CC
transfer — The fourth phase of the clock
charge storage — During this phase of
charge storage — The third phase of the
and the negative side is connected to
2
transfer — Phase two of the clock
2
, in a no–load condition V
to C
are initially charged to V
+
1
3
, which is applied to the negative
, the V
CC
–
and V
1
from V
2
produces –V
.
–
. Since C
–
2
. Since C
DD
–
compared to V
are separately generated
© Copyright 2006 Sipex Corporation
+
storage capacitor. This
will show a decrease in
2
1
is 2 times V
2
is switched to V
+
CC
2
is connected to
+
in the negative
is at V
1
+
2
+
is switched
and V
2
CC
to the V
due to the
to GND,
. C
CC
CC
3
–
, the
.
, the
1
l
will
+
–
2
CC
SS
is
is
is
2