XR68C681J-F Exar Corporation, XR68C681J-F Datasheet
XR68C681J-F
Specifications of XR68C681J-F
Available stocks
Related parts for XR68C681J-F
XR68C681J-F Summary of contents
Page 1
FEATURES GENERAL DESCRIPTION ORDERING INFORMATION Pin Part No. Package APPLICATIONS Operating Temperature Part No. Range ...
Page 2
XR68C681 Figure 1. Block Diagram of the XR68C681 DUART Device ...
Page 3
PIN CONFIGURATION XR68C681CJ 44 Pin PLCC PIN DESCRIPTION Pin Number Pin Number Symbol (44 pin PLCC) (40 pin DIP) Type Description No Connect. LSB of Address Input. Input Port 3. Address Input. Input Port 1. Address Input. MSB of Address ...
Page 4
XR68C681 PIN DESCRIPTION (CONT’D) Pin Number Pin Number (44 pin PLCC) (40 pin DIP) Symbol Type Description Input Port 0. Read/Write Input. Data Transfer Acknowledge. Receiver Serial Data Input- Channel B. No Connect. Transmitter Serial Data Output - Channel B. ...
Page 5
PIN DESCRIPTION (CONT’D) Pin Number Pin Number (44 pin PLCC) (40 pin DIP) Symbol Type Description Output 7. Three State Data Bus. Three State Data Bus. Three State Data Bus. MSB of Eight Bit Three State Data Bus. Ground. No ...
Page 6
XR68C681 PIN DESCRIPTION (CONT’D) Pin Number Pin Number (44 pin PLCC) (40 pin DIP) Symbol Type Description Transmitter Serial Data Output. No Connect. Receiver Serial Data Input. Crystal Output or External Clock Input. Crystal Input. Master Reset. Chip Select. Input ...
Page 7
PIN DESCRIPTION (CONT’D) Pin Number Pin Number (44 pin PLCC) (40 pin DIP) Symbol Type Description Input 5. Input 4. XR68C681 ...
Page 8
XR68C681 DC ELECTRICAL CHARACTERISTICS Test Conditions 70 Symbol Parameter Notes 1. Parameters are valid over the specified temperature and operating supply ranges. Typical values are 25C, V processing parameters. 2. All voltages are referenced ...
Page 9
AC ELECTRICAL CHARACTERISTICS Test Conditions 70 Symbol Parameter Rest Timing (See Figure 32) Read, Write and Interrupt Cycle Timing (Figure 33, Figure 34, Figure 35 ) Port Timing (Figure 36) Interrupt Output Timing (Figure ...
Page 10
XR68C681 AC ELECTRICAL CHARACTERISTICS Test Conditions 70 Symbol Parameter Clock Timing (Figure 38) Transmitter Timing (Figure 39) Receiver Timing (Figure 40) Notes 1. Parameters are valid over the specified temperature and operating supply ranges. ...
Page 11
SYSTEM DESCRIPTION PRINCIPLES OF OPERATION Figure XR68C681 A. DATA BUS BUFFER B. OPERATION CONTROL BLOCK B.1 DUART REGISTER ADDRESSING Table 1 ...
Page 12
XR68C681 ...
Page 13
Read Mode Registers Address Register Name (HEX) Table 1. DUART Port And Register Addressing Note: The shaded blocks are not Read/Write registers but rather, “Address-Triggered” Commands. Write Mode Registers Symbol Register Name XR68C681 Symbol ...
Page 14
XR68C681 Table 1 Bit 7 Bit 6 Bit 5 Miscellaneous Commands Section G.3 B.2 COMMAND DECODING Bit 4 Bit 3 Enable/Disable Transmitter Table 2. Command Register - CRA, CRB Bit 2 Bit 1 Bit 0 Enable/Disable Receiver Table 3 ...
Page 15
Bit 7 Bit 6 Bit 5 Bit 4 Table 3. Miscellaneous Commands, Upper Nibble of all Command Registers, Unless Otherwise Specified. Description Null Command: Reset MRn Pointer: Reset Receiver: Reset Transmitte Reset Error Status: Reset Break Change Interrupt: Start Break: ...
Page 16
XR68C681 Table Table 1 Section D.2 Register Description Table 4. Listing and Brief Description of Interrupt Control Block Registers C.1 Interrupt Status Registers (ISR) Section F C. INTERRUPT CONTROL BLOCK ...
Page 17
Bit 7 Bit 6 Bit 5 Input Port Delta Break RXRDY/ Change B FFULLB Table 5. Interrupt Status Register - (ISR) Bit Format ISR[7]: Input Port Change of State Section E ISR[6] Delta Break Indicator - Channel B: ...
Page 18
XR68C681 ISR[3] Counter Ready ISR[2]: Delta Break Indicator - Channel A Section G.2 ISR[1] RXRDYA/FFULLA - Channel A Receiver Ready or FIFO Full Bit 7 Bit 6 Bit 5 Input Port Delta Break RXRDY/ Change B FFULLB ISR[0]: Channel A ...
Page 19
C.3 Masked Interrupt Status Register (MISR) C.4 Interrupt Vector Register, IVR XR68C681 C.5 Limitations of the DUART Interrupt Structure C.6 Servicing DUART Interrupts ...
Page 20
XR68C681 XR68C681 Figure 2. Simple Illustration Depicting the Interfacing of the XR68C681 DUART to a 68000 Processor Figure 2 MC68000 Processor ...
Page 21
Figure 3 XR68C681 ...
Page 22
XR68C681 Figure 3. Detailed Schematics of the XR68C681 Interfacing to the 68000 Processor ...
Page 23
Figure 4 Figure 4. XR68C681/68000 CPU Interrupt Cycle Timing Interrupt Service Routine Section C.1 XR68C681 D. TIMING CONTROL BLOCK ...
Page 24
XR68C681 Figure 5. Block Diagram of DUART Timing Control Block Figure 5 D.1 Oscillator Circuit: Figure 6 Figure 7 Table 3 ...
Page 25
Figure 6. A Recommended Schematic for the XTAL Oscillator Circuitry Note: The user also has an option to drive the oscillator circuit with a TTL input signal, in lieu of using a crystal oscillator. If this approach is used, the ...
Page 26
XR68C681 D.2 Bit Rate Generator Figure 8. Block Diagram of the Bit Rate Generator Portion of the Timing Control Block Section D.5 Figure 8 ...
Page 27
D.3 Counter/Timer Figure 9 Bit 6 Bit 5 Bit 4 C/T Mode Table 7. ACR[6:4] Bit Field Definition - C/T Figure 9. A Block Diagram of the Circuitry Associated with the Counter/Timer Timing Source XR68C681 Table 7 ...
Page 28
XR68C681 D.3.1 Timer Mode: C/T Output Frequency = fsts • CTUR • + where The frequency of the selected timing source (See STS ) Table 7 [CTUR] = the contents of the CTUR register in decimal form [CTLR] ...
Page 29
D.4 External Inputs Section E Bit 7 Bit 6 Bit 5 Table 9 Table 8. Bit Format of the Clock Select Registers, CSRA and CSRB Field CSR[7:4] CSR[3:0] Table 9. Bit Format of the Clock Select Registers CSR[3:0] and CSR[7:4] ...
Page 30
XR68C681 Table Register Table 10. Command Register Control Over the Extend Bit Note: if the user programs either nibble of the Clock Select Register (CSRn[7:4] or CSRn[3:0]) with values 16 16 ranging from ...
Page 31
Transmitter T X Figure 10. Example of a Serial Data Transmission System Figure 11. Receiver (1X) Sampling, if the R Figure 11 Receiver Clock R Clock X clock is slightly faster X than the T clock. ...
Page 32
XR68C681 Received Data Actual Data Figure 12. Illustration of an Error Due to Receiver Drift. Figure Figure 13 ...
Page 33
Figure 13. The Typical Sampling Pattern of each Receiver within the XR68C681 Device. D.7 Application Examples using the Timing Control Block Example A: Using the BRG XR68C681 Table 9 Table 8 Table 9 ...
Page 34
XR68C681 Example B: Programming the Bit Rate via the Counter/Timer Example C: Using the External Input Ports ...
Page 35
D.8 Explanation of Clock Timing Signals Symbol Parameter Table 11. The XR68C681 Data Sheet presents the following parameter specifications, in the t - X1/CLK (External) High or Low Time CLK f - X1/CLK Crystal High or Low Time CLK t ...
Page 36
XR68C681 f - RXC and TXC (External) Frequency - via IP2, RTX IP3, IP4, and IP5 E. INPUT PORT E.1 Alternate Functions for the Input Port Table 12 ...
Page 37
Input Alternate Function(s) Port Table 12. Listing of Alternate Function for the Input Port Pins E.2 Input Port Configuration Registers (IPCR) Bit 7 Bit 6 Bit 5 Table 13. Bit Format of the Input Port Configuration Register (IPCR) Approach to ...
Page 38
XR68C681 Bits “Change in Logic State” Identification Bits Bits “The Current State of Input Pins IP0 - IP3” Bit 7 Bit 6 Bit 5 BRG Set Counter/Timer Mode and ...
Page 39
F. OUTPUT PORT Table 1 Table 1 XR68C681 F.1 Writing Data to the OPR/Output Port Pins F.1.1 SET OUTPUT PORT BITS COMMAND Figure 14. ...
Page 40
XR68C681 Figure 14. Illustration of the “SET OUTPUT PORT BIT” Command and its Effect on the Output Port Register and the State of the Output Port Pins. F.1.2 CLEAR OUTPUT PORT BITS COMMAND State of Output Port Pins (OP7 - ...
Page 41
Figure 15. Illustration of the “CLEAR OUTPUT PORT BIT” Command and its Effect on the Output Port Register and the State of the Output Port Pins. XR68C681 State of Output Port Pins (OP7 - OP0) F.2 Output Port Configuration Register ...
Page 42
XR68C681 Output Port RTSA: RTSB: TXCA_16X Output: TXCA_1X Output: RXCA_1X: Output: TXCB_1X Output: RXCB_1X Output: C/T_1_RDY: when used as the Counter/Timer Ready Output. RXRDY/FFULL_A Output: RXRDY/FFULL_B Output: TXRDY_A Output: TXRDY_B Output: Table 15. Listing of the Alternate Functions for the ...
Page 43
Section B.2 Figure 16. A Simplified Drawing depicting the Transmit Shift Regis- G.1 Transmitter (TSR and THR) ter and the Transmit Holding Register. XR68C681 Section D Figure 16 ...
Page 44
XR68C681 Figure 17. The Output Waveform of the Transmitter Table 2 Section B.2 while sending 5D (8-N-1 protocol). 16 G.2 Receiver (RSR and RHR) Figure 17 Figure 18 ...
Page 45
Figure 18. A Simplified Drawing of the Receiver Shift Register and Receiver Holding Register XR68C681 ...
Page 46
XR68C681 Receiver Errors Bit 7 Bit 6 Bit 5 Rx RTS Rx Interrupt Error Mode Control Select Select Table 17. The Bit Format for Mode Registers MR1A and MR1B G.3 Mode Registers, MR1n and MR2n Bit 4 Bit 3 Bit ...
Page 47
Bit 7 Bit 6 Bit 5 Channel Mode Tx RTS Control Table 18. The Bit Format for Mode Registers MR2A and MR2B MR1n[7] - Receiver Request to Send Control Figure 24 MR1n[6] - Receiver Interrupt Select Bit 4 Bit 3 ...
Page 48
XR68C681 MR1n[2] - Parity Type Select MR1n[1:0] - Bits per Character Select Figure 19. A Block Diagram Depicting Normal Mode Operation Mode Register 2 (Channels A and B) MR2n[7:6] - Channel Mode Select Figure 19 ...
Page 49
Figure 20 Figure 20. A Block Diagram Depicting “Automatic Echo Mode” Operation XR68C681 Local Loopback Mode Figure 21 ...
Page 50
XR68C681 Figure 21. A Block Diagram Depicting “Local Loopback Mode” Operation ...
Page 51
Remote Loopback Mode Note: The CPU has no access to the Serial Data during Remote Loopback Mode. Figure 22. A Block Diagram Depicting “Remote Loopback Mode” Operation MR2n[5] - Transmitter Request-to-Send Control Figure 22 Figure 26 MR2n[4] - Clear to ...
Page 52
XR68C681 Figure 24 Figure 26 MR2n[3:0] - Stop Bit Length Bit 7 Bit 6 Bit 5 Received Framing Parity Error Break Error Table 19. The Bit Format of the Status Register’s SRA and SRB SRn[7] Received Break G.4 Status Register, ...
Page 53
Table 2 SRn[5] Parity Error Table 2 SRn[4] Overrun Error XR68C681 SRn[3] Transmitter Empty (TXEMT) SRn[2] Transmitter Ready (TXRDY) SRn[1] FIFO Full (FFULL) SRn[0] Receiver Ready (RXRDY ...
Page 54
XR68C681 H. SPECIAL MODES OF OPERATION H.1 RTS/CTS Handshaking Receiving Device Figure 23. Block Diagram and Timing Sequence of Two DUARTs Connected in the Receiver-RTS Controlled Configuration. H.1.1 Receiver-Controlled RTS/CTS Handshaking Transmitting Device Figure 23 ...
Page 55
Figure 23 Section G.3 Section G.3 XR68C681 Figure 23 Figure 24 ...
Page 56
XR68C681 Figure 24. A Flow Diagram Depicting an Algorithm That Could be Used to Apply the Receiver-Controlled RTS/CTS Handshaking Mode H.1.2 Transmitter-Controlled RTS/CTS Handshaking ...
Page 57
Transmitting Device TXRDY_A (OP7) To CPU TXRDY_A RTSA CTSA RXDA Figure 25. Block Diagram and Timing Sequence of Two DUARTs Connected in the Transmitter-RTS Controlled Configuration. Figure 25 Section G.3 Receiving Device IP2 RTSA (OP0) (RTS-in) OP3 CTSA (IP0) (CTS-out) ...
Page 58
XR68C681 Figure 26. A Flow Diagram Depicting an Algorithm That Could be Used to Realize the Transmitter-Controlled RTS/CTS Handshaking Mode H.2 Multi-drop (8051 9 bit) Mode H.2.1 Concept of Multi-Drop Mode Figure 27 ...
Page 59
Figure 27. An Illustration Depicting the Concept of Multi-Drop Mode Figure 28. Bit Format of Character Data Being Transmitted in Figure 28 the Multi-Drop Mode H.2.2 DUART Multi-Drop Operation Transmitter Operation During Multi-Drop Mode Figure 29 XR68C681 ...
Page 60
XR68C681 Figure 29. A Flow Diagram Depicting a Procedure That Can be Used to Receiver Operation during Multi-Drop Mode Transmit Characters in the Multi-Drop Mode. ...
Page 61
Figure 30 Figure 30. A Flow Diagram Depicting a Procedure That Can be Used to Receive Characters in the Multi-Drop Mode. H.3 Standby Mode XR68C681 • ...
Page 62
XR68C681 I. PROGRAMMING Table 1 Bit 7 Bit 6 Bit 5 Rx RTS Rx Int Select Error Mode Control Bit 7 Bit 6 Bit 5 Channel Mode Tx RTS Control Bit 7 Bit 6 Bit 5 Table 6 Table 22. ...
Page 63
Bit 7 Bit 6 Bit 5 Miscellaneous Commands Section B.2 Table 23. Command Registers: CRA, CRB Bit 7 Bit 6 Bit 5 Received Framing Parity Error Break Error Table 24. Status Registers: SRA, SRB Bit 7 Bit 6 Bit 5 ...
Page 64
XR68C681 Bit 7 Bit 6 Bit 5 Input Port Delta Break RXRDY/ Change B FFULLB Bit 7 Bit 6 Bit 5 Input Port Delta Break RXRDY/ Change B FFULLB Bit 7 Bit 6 Bit 5 Table 30. Counter/Timer Upper Byte ...
Page 65
XR68C681 ...
Page 66
XR68C681 J. Timing Diagrams Figure 31. Input and Output Levels for Timing Measurements Note: AC testing inputs are driven at 0.4V for a logic “0” and 2.4V for a logic “1” except for -40 to 85C and -55 to 125C, ...
Page 67
Figure 33. XR68C681 Read Cycle Timing XR68C681 ...
Page 68
XR68C681 Figure 34. XR68C681 Write Cycle Timing ...
Page 69
Figure 35. XR68C681 Interrupt Cycle Timing XR68C681 ...
Page 70
XR68C681 Figure 36. Port Timing Figure 37. Interrupt Timing ...
Page 71
Figure 38. Clock Timing XR68C681 ...
Page 72
XR68C681 Figure 39. Transmitter Timing Figure 40. Receiver Timing ...
Page 73
LEAD PLASTIC LEADED CHIP CARRIER SYMBOL Note: The control dimension is the inch column (PLCC) Rev. 1. INCHES MILLIMETERS MIN MAX MIN ...
Page 74
XR68C681 40 LEAD CERAMIC DUAL-IN-LINE A Base 1 Plane Seating L Plane B SYMBOL Note: The control dimension is the inch column (600 MIL CDIP) Rev. 1. INCHES MILLIMETERS MIN MAX MIN MAX ...
Page 75
XR68C681 ...