ST16C654CJ68-F Exar Corporation, ST16C654CJ68-F Datasheet - Page 4

• Manufacturer Part Number: ST16C654CJ68-F
• Description: IC UART FIFO 64B QUAD 68PLCC
• Manufacturer: Exar Corporation
• Type: Quad UART with 64-byte FIFOsr

Specifications of ST16C654CJ68-F

• Number Of Channels: 4, QUART
• Package / Case: 68-LCC (J-Lead)
• Features: *
• Fifo's: 64 Byte
• Protocol: RS232
• Voltage - Supply: 2.97 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 1.5 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.97 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V, 5 V
• No. Of Channels: 4
• Uart Features: Infrared (IrDA) Encoder/Decoder
• Supply Voltage Range: 2.97V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: PLCC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1269-5

ST16C654/654D
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
PIN DESCRIPTIONS
Pin Description
DATA BUS INTERFACE
(R/W#)
(VCC)
CSC#
CSD#
(VCC)
IOW#
CSA#
(CS#)
CSB#
N
IOR#
(A3)
(A4)
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
AME
64-LQFP
P
22
23
24
60
59
58
57
56
55
54
53
40
38
42
11
IN
9
7
#
68-PLCC
P
32
33
34
68
67
66
52
18
16
20
50
54
IN
5
4
3
2
1
#
100-QFP
P
37
38
39
95
94
93
92
91
90
89
88
66
15
13
17
64
68
IN
#
T
I/O
YPE
I
I
I
I
I
I
I
Address data lines [2:0]. These 3 address lines select one of the
internal registers in UART channel A-D during a data bus transac-
tion.
Data bus lines [7:0] (bidirectional).
When 16/68# pin is at logic 1, the Intel bus interface is selected and
this input becomes read strobe (active low). The falling edge insti-
gates an internal read cycle and retrieves the data byte from an
internal register pointed by the address lines [A2:A0], puts the data
byte on the data bus to allow the host processor to read it on the ris-
ing edge.
When 16/68# pin is at logic 0, the Motorola bus interface is selected
and this input is not used and should be connected to VCC.
When 16/68# pin is at logic 1, it selects Intel bus interface and this
input becomes write strobe (active low). The falling edge instigates
the internal write cycle and the rising edge transfers the data byte on
the data bus to an internal register pointed by the address lines.
When 16/68# pin is at logic 0, the Motorola bus interface is selected
and this input becomes read (logic 1) and write (logic 0) signal.
When 16/68# pin is at logic 1, this input is chip select A (active low)
to enable channel A in the device.
When 16/68# pin is at logic 0, this input becomes the chip select
(active low) for the Motorola bus interface.
When 16/68# pin is at logic 1, this input is chip select B (active low)
to enable channel B in the device.
When 16/68# pin is at logic 0, this input becomes address line A3
which is used for channel selection in the Motorola bus interface.
When 16/68# pin is at logic 1, this input is chip select C (active low)
to enable channel C in the device.
When 16/68# pin is at logic 0, this input becomes address line A4
which is used for channel selection in the Motorola bus interface.
When 16/68# pin is at logic 1, this input is chip select D (active low)
to enable channel D in the device.
When 16/68# pin is at logic 0, this input is not used and should be
connected VCC.
4
D
ESCRIPTION
xr
REV. 5.0.2