XR16L788CQ-F Exar Corporation, XR16L788CQ-F Datasheet - Page 9

• Manufacturer Part Number: XR16L788CQ-F
• Description: IC UART 64B 3.3V OCTAL 100QFP
• Manufacturer: Exar Corporation
• Type: IrDA or RS- 485r

Specifications of XR16L788CQ-F

• Number Of Channels: 8
• Package / Case: 100-BQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 2.97 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 6.25 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.97 V
• Supply Current: 5 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V or 5 V
• No. Of Channels: 8
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 2.97V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: QFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1283

REV. 1.2.3
A single Baud Rate Generator (BRG) is provided for the transmitter and receiver, allowing independent TX/RX
channel control. The programmable Baud Rate Generator is capable of operating with a crystal frequency of
up to 24 MHz. However, with an external clock input on XTAL1 pin and a 2K ohms pull-up resistor on XTAL2
pin (as shown in
temperature and 5.0V.
F
Each UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter and receiver. The
prescaler is controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide
the input crystal or external clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG further
divides this clock by a programmable divisor between 1 and (2
the serial data rate. The sampling clock is used by the transmitter for data bit shifting and receiver for data
sampling. The BRG divisor (DLL and DLM registers) defaults to a random value upon power up. Therefore, the
BRG must be programmed during initialization to the operating data rate.
2.6
IGURE
4. E
Programmable Baud Rate Generator
XTERNAL
F
IGURE
XTAL1
XTAL2
Figure
5. B
C
LOCK
4) it can extend its operation up to 50 MHz (3.125 Mbps serial data rate) at room
AUD
C
Crystal
R
Buffer
ONNECTION FOR
Osc/
ATE
G
Channels
To Other
ENERATOR
vcc
gnd
External Clock
Divide by 4
Divide by 1
Prescaler
Prescaler
E
XTENDED
R1
2K
VCC
9
HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART
D
MCR Bit-7=0
MCR Bit-7=1
ATA
XTAL1
XTAL2
(default)
R
16
ATE
-1) to obtain a 16X or 8X sampling clock of
DLL and DLM
Baud Rate
Generator
Registers
Logic
Rate Clock to
and Receiver
Transmitter
16X or 8X
Sampling
XR16L788