71M6521DE-IM/F Maxim Integrated Products, 71M6521DE-IM/F Datasheet - Page 41

• Manufacturer Part Number: 71M6521DE-IM/F
• Description: IC ENERGY METER 16K FLASH 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 71M6521DE-IM/F

• Mounting Style: SMD/SMT
• Package / Case: QFN-68
• Program Memory Size: 16 KB
• Program Memory Type: Flash
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

71M6521DE/DH/FE Data Sheet
Additionally, if DIO6 and DIO7 are declared outputs, they can be configured as dedicated pulse outputs (WPULSE =
DIO6, VARPULSE = DIO7) using DIO_PW and DIO_PV registers. In this case, DIO6 and DIO7 are under CE control.
DIO4 and DIO5 can be configured to implement the EEPROM Interface.
The PB pin is a dedicated digital input. If the optical UART is not used, OPT_TX and OPT_RX can be configured as
dedicated DIO pins (DIO1, DIO2, see Optical Interface section).
A 3-bit configuration word, I/O RAM register, DIO_Rx (0x2009[2:0] through 0x200E[6:4]) can be used for certain pins,
when configured as DIO, to individually assign an internal resource such as an interrupt or a timer control (see Table
54 for DIO pins available for this option). This way, DIO pins can be tracked even if they are configured as outputs.
driver.
The control resources selectable for the DIO pins are listed in Table 56. If more than one input is connected to the
same resource, the resources are combined using a logical OR.
The PB pin is a dedicated digital input. In addition, if the optical UART is not used, OPT_TX and OPT_RX can be
configured as dedicated DIO pins. Thus, in addition to the 16 general-purpose DIO pins (DIO4…DIO11,
DIO14…DIO21), there are three additional pins that can be used for digital input and output.
Rev 2
DIO
Pin no. (64 LQFP)
Pin no. (68 QFN)
Data Register
Direction Register
Internal Resources
Configurable
DIO
Pin no. (64 LQFP)
Pin no. (68 QFN)
Data Register
Direction Register
Internal Resources
Configurable
Tracking DIO pins configured as outputs is useful for pulse counting without external hardware.
When driving LEDs, relay coils etc., the DIO pins should sink the current into GNDD (as shown in
When configured as inputs, the dual-function (DIO/SEG) pins should not be pulled above V3P3SYS
in MISSION and above VBAT in LCD and BROWNOUT modes. Doing so will distort the LCD
waveforms of the other pins. This limitation applies to any pin that can be configured as a LCD
Figure 8, right), not source it from V3P3D (as shown in Figure 8, left). This is due to the resistance
of the internal switch that connects V3P3D to either V3P3SYS or VBAT.
Table 54: Data/Direction Registers and Internal Resources for DIO Pin Groups
PB
62
65
16
22
23
Y
N
0
0
0
0
DIO Pin n Function
57
60
17
12
13
N
Y
1
1
1
1
1
DIO_DIR0 (SFR 0xA2)
DIO_DIR2 (SFR 0xA1)
DIO2=P2 (SFR 0xA0)
DIO0=P0 (SFR 0x80)
18
Y
--
--
--
--
--
2
3
3
2
2
Table 55: DIO_DIR Control Bit
19
24
N
Y
--
3
5
3
3
3
3
-
37
39
20
47
N
4
4
4
Y
--
4
4
38
40
21
68
N
5
5
5
Y
--
5
5
Input
39
41
22
Y
--
--
--
--
6
6
6
0
DIO_DIR [n]
40
42
23
Y
--
--
--
--
7
7
7
41
43
Y
8
0
0
Output
1
42
44
Y
9
1
1
DIO_DIR1 (SFR 0x91)
DIO1=P1 (SFR 0x90)
10
43
45
Y
2
2
11
44
46
Y
3
3
12
--
--
--
--
--
13
--
--
--
--
--
14
20
21
--
6
6
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