78M6612-IMR/F Maxim Integrated Products, 78M6612-IMR/F Datasheet
78M6612-IMR/F
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... TM Simplifying System Integration DESCRIPTION The Teridian 78M6612 is a highly integrated, single-phase, power and energy measurement and monitoring SOC which includes a 32-bit compute engine (CE), an MPU core, RTC, and Flash. The Teridian patented Single ® Converter Technology with a 22-bit delta-sigma ADC, 4 analog inputs, digital temperature compensation, and ...
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... MPU Core .................................................................................................................. 16 1.4.1 Memory Organization ................................................................................................. 17 1.4.2 Special Function Registers (SFRs) ............................................................................ 19 1.4.3 Special Function Registers (Generic 80515 SFRs) .................................................... 20 1.4.4 Special Function Registers Specific to the 78M6612 ................................................. 22 1.4.5 Instruction Set ........................................................................................................... 24 1.4.6 UARTs ....................................................................................................................... 24 1.4.7 Timers and Counters ................................................................................................. 27 1.4.8 WD Timer (Software Watchdog Timer) ....................................................................... 29 1.4.9 Interrupts ................................................................................................................... 31 1 ...
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... VREF, VBIAS ............................................................................................................ 95 5.4.11 LCD Drivers ............................................................................................................... 95 5.4.12 ADC Converter, V3P3A Referenced .......................................................................... 96 5.4.13 UART1 Interface ........................................................................................................ 96 5.4.14 Temperature Sensor .................................................................................................. 96 5.5 Timing Specifications ............................................................................................................ 97 5.5.1 RAM and Flash Memory ............................................................................................ 97 5.5.2 Flash Memory Timing ................................................................................................ 97 5.5.3 EEPROM Interface .................................................................................................... 97 5.5.4 RESET and V1 .......................................................................................................... 97 5.5.5 RTC ........................................................................................................................... 97 Rev. 1.2 78M6612 Data Sheet 3 ...
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... Data Sheet 5.5.6 Typical Performance Data .......................................................................................... 98 6 Packaging .................................................................................................................................. 100 6.1 64 LQFP Package ............................................................................................................... 100 6.1.1 Pinout ...................................................................................................................... 100 6.1.2 Package Outline (LQFP 64) ..................................................................................... 101 6.1.3 Recommended PCB Land Pattern for the LQFP-64 Package .................................. 102 6.2 68-Pin QFN Package .......................................................................................................... 103 6.2.1 Pinout ...................................................................................................................... 103 6.2.2 Package Outline ...................................................................................................... 104 6 ...
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... Figure 39: Wh Accuracy 120 V/60 Hz and Room Temperature Using a 4 mΩ Current Shunt ..................................................................................................... 98 Figure 40: Measurement Accuracy over Harmonics at 240 V, 30A per IEC62053-2x Section 8.2.1 ........................................................................................................................... 98 Figure 41: Typical Measurement Accuracy over Temperature Relative to 25°C ...................................... 99 Figure 42: 64-Pin LQFP Pinout ........................................................................................................... 100 Figure 43: 68-Pin QFN Pinout ............................................................................................................. 103 Rev. 1.2 78M6612 Data Sheet 5 ...
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... Data Sheet Tables Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles ....................................................... 9 Table 2: CE DRAM Locations for ADC Results ...................................................................................... 12 Table 3: Memory Map ............................................................................................................................ 17 Table 4: Stretch Memory Cycle Width .................................................................................................... 18 Table 5: Internal Data Memory Map ....................................................................................................... 19 Table 6: Special Function Registers Locations ....................................................................................... 19 Table 7: Special Function Registers Reset Values ................................................................................. 20 Table 8: PSW Register ...
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... PROG MEMORY 0000-7FFF SHARE CE_LCTN MPU_RSTZ EMULATOR PORT E_RXTX E_TCLK E_RST (Open Drain) RESET E_RXTX/SEG38 E_TCLK/SEG33 E_RST/SEG32 Figure 1: IC Functional Block Diagram 78M6612 Data Sheet V3P3A GNDA V3P3SYS V3P3D V3P3D VBAT VBAT VOLT REG GNDD LCD_ONLY SLEEP V2P5 2.5V to logic V3P3D ...
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... MPU, processed further and output using the peripheral devices available to the MPU. In addition to advanced measurement functions, the real time clock function allows the 78M6612 to record time of use (TOU) measurement information for multi-rate applications and to time-stamp events. ...
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... DS_6612_001 1.2 Analog Front End (AFE) The AFE of the 78M6612 is comprised of an input multiplexer, a delta-sigma A/D converter and a voltage reference. 1.2.1 Input Multiplexer The input multiplexer supports up to four input signals that are applied to pins IA, VA, IB and VB of the device. Additionally, using the alternate mux selection, it has the ability to select temperature and the battery voltage. The multiplexer can be operated in two modes: • ...
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... Data Sheet Initiation of each ADC conversion is controlled by the multiplexer control circuit as described previously. At the end of each ADC conversion, the FIR filter output data is stored into the CE DRAM location determined by the multiplexer selection. 1.2.3 FIR Filter The finite impulse response filter is an integral part of the ADC and it is optimized for use with the multiplexer ...
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... The internal bias voltage VBIAS (typically 1 used by the ADC when measuring the temperature and battery monitor signals. 1.2.5 Temperature Sensor The 78M6612 includes an on-chip temperature sensor implemented as a bandgap reference used to determine the die temperature The MPU may request an alternate multiplexer cycle containing the temperature sensor output by asserting MUX_ALT. ...
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... Data Sheet 1.3 Digital Computation Engine (CE) The CE, a dedicated 32-bit signal processor, performs the precision computations necessary to accurately measure energy. The CE calculations and processes include: • Multiplication of each current sample with its associated voltage sample to obtain the energy per sample (when multiplied with the constant sample time). ...
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... DS_6612_001 The CE of the 78M6612 is aided by support hardware that facilitates implementation of equations, pulse counters, and accumulators. This support hardware is controlled through I/O RAM locations EQU (equation assist), DIO_PV and DIO_PW (pulse count assist), and PRE_SAMPS and SUM_CYCLES (accumulation assist). PRE_SAMPS and SUM_CYCLES support a dual level accumulation scheme where the first accumulator accumulates results from PRE_SAMPS samples and the second accumulator accumulates up to SUM_CYCLES of the first accumulator results ...
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... Data Sheet If the pulse period corresponding to the pulse rate exceeds the desired pulse width, a square wave with 50% duty-cycle is generated. The CE pulse output polarity is programmable to be either positive or negative. Pulse polarity may be inverted with PLS_INV. When this bit is set, the pulses are active high, rather than the more usual active low ...
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... DS_6612_001 Figure 5 shows the accumulation interval resulting from PRE_SAMPS = 42 and SUM_CYCLES = 50, consisting of 2100 samples of 397µs each, followed by the XFER_BUSY interrupt. The sampling in this example is applied to a 50Hz signal. Rev. 1.2 Figure 5: Accumulation Interval 78M6612 Data Sheet 15 ...
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... MPU Core The 78M6612 includes an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one clock cycle. Using a 5 MHz (4.9152 MHz) clock results in a processing throughput of 5 MIPS. The 80515 architecture eliminates redundant bus states and implements parallel execution of fetch and execution phases ...
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... Static RAM Internal and External Data Memory: Both internal and external data memory are physically located on the 78M6612 IC. “External” data memory is defined as external to the 80515 MPU core. Program Memory: The 80515 can theoretically address program memory space from 0x0000 to 0xFFFF. Program memory is read when the MPU fetches instructions or performs a MOVC operation ...
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... Data Sheet CKCON Register CKCON[2] CKCON[1] CKCON[ There are two types of instructions, differing in whether they provide an eight-bit or sixteen-bit indirect address to the external data RAM. In the first type (MOVX A,@Ri), the contents R1, in the current register bank, provide the eight lower-ordered bits of address. The eight high-ordered bits of address are specified with the USR2 This method allows the user paged access (256 pages of 256 bytes each) to all ranges of the external data RAM ...
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... P0 SP Only a few addresses are occupied, the others are not implemented. SFRs specific to the 78M6612 are shown in bold print. Any read access to unimplemented addresses will return undefined data, while any write access will have no effect. The registers at 0x80, 0x88, 0x90, etc., are bit-addressable, all others are byte-addressable ...
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... Data Sheet 1.4.3 Special Function Registers (Generic 80515 SFRs) shows the location of the SFRs and the value they assume at reset or power-up. Table 7 Table 7: Special Function Registers Reset Values Name Location Reset Value Description 0x80 0xFF P0 0x81 0x07 SP DPL 0x82 0x00 ...
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... Bank 1 10 Bank 2 11 Bank 3 DPTR bytes wide. The lower part is DPL, and the highest is DPH PC bytes wide and initialized to 0x0000 after reset. This 78M6612 Data Sheet LSB – P RS1 and RS0 select the Location (0x00 – 0x07) (0x08 – 0x0F) (0x10 – ...
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... DIO pins that are under CE control. The technique of reading the status of or generating interrupts based on DIO pins configured as outputs, can be used to implement pulse counting. 1.4.4 Special Function Registers Specific to the 78M6612 Table 10 shows the location and description of the 78M6612-specific SFRs. Alternative SFR Register Name ...
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... Write 0: Clears the PLL_FALL interrupt flag. Write 1: Resets the watch dog timer . R Interrupt inputs. The MPU may read these bits to see the input to external interrupts INT0, INT1 INT6. These bits do not have any memory and are primarily intended for debug use. 78M6612 Data Sheet for a 23 ...
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... All instructions of the generic 8051 microcontroller are supported. A complete list of the instruction set and of the associated op-codes is contained in the Teridian 78M6612 Firmware Developer’s Manual. 1.4.6 UARTs The 78M6612 includes a UART (UART0) that can be programmed to communicate with a variety of external devices. A second UART (UART1) is connected to the optical port, as described in 1.5.6 Optical Interface ...
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... UART 0 2 9-bit UART 1 3 9-bit UART 1 th transmitted data bit in Modes 2 and 3. Set or cleared by the MPU, th data bit received. In Mode 1, if SM20 the stop bit. In mode 0 this bit is not used. Must be cleared by 78M6612 Data Sheet th bit, . LSB TI0 RI0 SM1 ...
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... Data Sheet Serial Interface 1 Control Register (S1CON) The function of the serial port depends on the setting of the Serial Port Control Register S1CON MSB – SM Bit Symbol Function Sets the baud rate for UART1 S1CON[7] SM Enables the inter-processor communication feature. S1CON[5] SM21 If set, enables serial reception ...
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... Four operating modes can be selected for Timer 0 and Timer 1. Two Special Function Registers (TMOD and TCON) are used to select the appropriate mode. Rev. 1.2 Register ) TCON Table 15: The Register TCON TF0 TR0 IE1 IT1 78M6612 Data Sheet LSB IE0 IT0 27 ...
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... Data Sheet Timer/Counter Mode Control Register (TMOD Bits TR1 (TCON[6]) and TR0 (TCON[4]) in the TCON when set. MSB GATE C/T Timer 1 Bit Symbol Function If set, enables external gate control (pin int0 or int1 for Counter TMOD[7] respectively). When int0 or int1 is high, and TRX bit is set (see TCON ...
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... WDT resets. Teridian strongly discourages the use of the software WDT. Rev. 1.2 Table 19: The PCON Register – – – – ), prescalers (by 2 and by 16), and control logic. Once 78M6612 Data Sheet LSB – – flag. When the WDT register 29 ...
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... Data Sheet Special Function Registers for the WD Timer Interrupt Enable 0 Register (IEN0 MSB EAL WDT Bit Symbol Function Watchdog timer refresh flag. IEN0[6] WDT Set to initiate a refresh of the watchdog timer. Must be set directly before SWDT is set to prevent an unintentional refresh of the watchdog timer. ...
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... SFRs IEN0, IEN1, and IEN2 . External interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of the 78M6612, for example the CE, DIO, RTC EEPROM interface. 1.4.9.1 Interrupt Overview When an interrupt occurs, the MPU will vector to the predetermined address as shown in Once interrupt service has begun, it can be interrupted only by a higher priority interrupt ...
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... Data Sheet Special Function Registers for Interrupts The following SFR registers control the interrupt functions: • The interrupt enable Registers: IEN0, IEN1 and IEN2 (see • The Timer/Counter control registers: The Timer/Counter control registers: TCON and T2CON Table 27 and Table 28). • ...
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... Polarity control for INT3: 0 – falling edge, 1 – rising edge. TCON[4] – Not used. … T2CON[0] Rev. 1.2 ) Table 26: The Register IEN2 – – – ) TCON Table 27: The TCON Register TF0 TR0 IE1 IT1 Table 28: The T2CON Bit Functions 78M6612 Data Sheet LSB – – ES1 LSB IE0 IT0 33 ...
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... External Interrupts The 78M6612 MPU allows seven external interrupts. These are connected as shown in direction of interrupts 2 and 3 is programmable in the MPU. Interrupts 2 and 3 should be programmed for falling sensitivity. The generic 8051 MPU literature states that interrupt 4 through 6 are defined as rising edge sensitive ...
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... SFRE8[5] IE_WAKE Table 31 because it behaves similarly to interrupt flags, even though Table 31. The polarity of interrupts 2 and Interrupts 2 and 3 should be Table 31 . 78M6612 Data Sheet Interrupt Description External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 XFER_BUSY interrupt (int 6) ...
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... Data Sheet SFR (special function register) enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its own flag bit that is set by the interrupt hardware and is reset automatically by the MPU interrupt handler (0 through 5). XFER_BUSY and RTC_1SEC have their own enable and flag bits in addition to the interrupt 6 enable and flag bits, and these interrupts must be cleared by the MPU software ...
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... Level3 (highest) Table 36: Interrupt Polling Sequence External interrupt 0 Serial channel 1 interrupt Timer 0 interrupt External interrupt 2 External interrupt 1 External interrupt 3 Timer 1 interrupt External interrupt 4 Serial channel 0 interrupt External interrupt 5 External interrupt 6 78M6612 Data Sheet LSB IP0[2] IP0[1] IP0[0] LSB IP1[2] IP1[1] IP1[0] 37 ...
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... Data Sheet 1.4.9.4 Interrupt Sources and Vectors Table 37 shows the interrupts with their associated flags and vector addresses. Interrupt Request Flag Description IE0 TF0 IE1 TF1 RI0/TI0 RI1/TI1 IEX2 IEX3 IEX4 IEX5 IEX6 38 Table 37: Interrupt Vectors Interrupt Vector Address External interrupt 0 ...
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... Logic and Interrupt Polarity Control Selection IEN0[7] Register >=1 I2F IRCON[1] R I3F IRCON[2] R IRCON[3] >=1 IRCON[4] IRCON[5] Figure 6: Interrupt Structure 78M6612 Data Sheet Interrupt Priority Enable Assignment IEN0[0] IP1[0]/ IP0[0] IEN2[0] Polling Sequence IEN0[1] Interrupt IP1[1]/ IEN1[1] Vector IP0[1] IEN0[2] IP1[2]/ IEN1[2] ...
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... On-Chip Resources 1.5.1 Oscillator The 78M6612 oscillator drives a standard 32.768 kHz watch crystal. These crystals are accurate and do not require a high-current oscillator circuit. The 78M6612 oscillator has been designed specifically to handle these crystals and is compatible with their high impedance and limited power handling capability. ...
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... Compensation). 1.5.5 Physical Memory Flash Memory: The 78M6612 includes on-chip Flash memory. The Flash memory primarily contains MPU and CE program code. It also contains images of the CE DRAM, MPU RAM, and I/O RAM. On power-up, before enabling the CE, the MPU copies these images to their respective locations. ...
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... RAM and then written back to the Flash memory. MPU RAM: The 78M6612 includes 2k-bytes of static RAM memory on-chip (XRAM) plus 256-bytes of internal RAM in the MPU core. The 2K-bytes of static RAM are used for data storage during normal MPU operations ...
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... DIO2=P2 1 – – – (SFR 0xA1) DIO_DIR2 N – – – 78M6612 Data Sheet Table 38 lists the Table 39 shows the con – – – – – – 6 (SFR 0x90) DIO1= – – ...
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... Data Sheet DIO Pin n Function Additionally, if DIO6 and DIO7 are declared outputs, they can be configured as dedicated pulse outputs (WPULSE = DIO6, VARPULSE = DIO7) using DIO_PW and DIO_PV registers. In this case, DIO6 and DIO7 are under CE control. DIO4 and DIO5 can be configured to implement the EEPROM Interface. ...
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... T0 (counter0 clock) T1 (counter1 clock) High priority I/O interrupt (INT0 rising) Low priority I/O interrupt (INT1 rising) High priority I/O interrupt (INT0 falling) Low priority I/O interrupt (INT1 falling) Section 5.4.4 Battery Monitor for details regarding the ADC LSB size 78M6612 Data Sheet 45 ...
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... Data Sheet 1.5.10 EEPROM Interface The 78M6612 provides hardware support for a two-pin or a three-pin EEPROM interface. The EEPROM interface uses the EECTRL and EEDATA registers for communication. 1.5.10.1 Two-Pin EEPROM Interface The dedicated 2-pin serial interface communicates with external EEPROM devices. The interface is multiplexed onto pins DIO4 (SCK) and DIO5 (SDA) controlled by the I/O RAM bits DIO_EEX[1:0] (see the I/O RAM Table) ...
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... CNT bits will be sent MSB first to EEPROM, shifted out of EEDATA’s MSB. If CNT is zero, SDATA will simply obey the HiZ bit. through Figure 13 describe the 3-wire EEPROM interface behavior. All CNT Cycles (6 shown (LoZ) 78M6612 Data Sheet Figure 9 through Figure 13 INT5 ...
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... Data Sheet EECTRL Byte Written Write -- With HiZ SCLK (output) SDATA (output) SDATA output Z BUSY (bit) Figure 10: 3-Wire Interface. Write Command, HiZ=1 EECTRL Byte Written READ SCLK (output) SDATA (input) SDATA output Z BUSY (bit) Figure 11: 3-Wire Interface. Read Command EECTRL Byte Written ...
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... Since there is no method in firmware to disable the crystal oscillator or the WDT guaranteed that whatever state the part might find itself in, upon WDT overflow, the part will be reset to a known state. Section 2.5 Wake Up 78M6612 Data Sheet for a Behavior). 49 ...
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... Data Sheet Specifically, when SECURE is set: • The ICE is limited to bulk Flash erase only. • Page zero of Flash memory, the preferred location for the user’s preboot code, may not be page-erased by either MPU or ICE. Page zero may only be erased with global Flash erase. ...
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... For a practical measurement, not only voltage and current amplitudes, but also phase angles and harmonic content may change constantly. Thus, simple RMS measurements are inherently inaccurate. A modern solid-state electricity Power and Energy Measurement IC such as the Teridian 78M6612 functions by emulating the integral operation above, i.e. it processes current and voltage samples through an ADC at a constant frequency ...
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... Data Sheet 2.2 System Timing Summary Figure 16 summarizes the timing relationships between the input MUX states, the CE_BUSY signal, and the two serial output streams. In this example, MUX_DIV[1: and FIR_LEN = 1 (384). The duration of each MUX frame MUX_DIV[1: FIR_LEN = 0 (288), and 1 + MUX_DIV[1: FIR_LEN (384) ...
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... PLL is stable. This mode is the normal operation mode where the part is capable of measuring energy. When system power is not available (i.e. when V1<VBIAS), the 78M6612 can be in one of three battery modes, i.e. BROWNOUT, LCD, or SLEEP mode. As soon as V1 falls below VBIAS or when the part ...
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... Data Sheet Circuit Function CE CE Data RAM FIR Analog circuits: PLL, ADC, VREF, BME etc MPU clock rate MPU_DIV ICE DIO Pins Watchdog Timer LCD EEPROM Interface (2-wire) EEPROM Interface (3-wire) UART Optical TX modulation Flash Read Flash Page Erase Flash Write ...
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... SLEEP mode. Rev. 1.2 MISSION RESET V3P3SYS falls IE_PLLRISE IE_PLLFALL V3P3SYS rises BROWNOUT RESET & VBAT_OK IE_WAKE SLEEP or VBAT_OK timer timer VBAT_OK RESET & VBAT_OK SLEEP 78M6612 Data Sheet V1 > VBIAS V1 <= VBIAS V3P3SYS rises VBAT_OK Figure 20 shows Figure 21 shows 55 ...
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... Data Sheet IA VA MUX VBIAS IB VB VBAT VREF TEMP VREF_CAL MUX VREF_DIS MUX CROSS CTRL EQU CK32 MUX_ALT CHOP_E MUX_DIV OSC RTCLK (32KHz) XIN (32KHz) XOUT CKTEST/ SEG19 4.9MHz CKOUT_E CK_GEN CK_2X ECK_DIS MPU_DIV MUX_SYNC CKCE <4.9MHz TEST TEST MODE ...
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... PROG MEMORY 0000-7FFF SHARE CE_LCTN MPU_RSTZ EMULATOR PORT E_RXTX E_TCLK E_RST (Open Drain) RESET E_RXTX/SEG38 E_TCLK/SEG33 E_RST/SEG32 78M6612 Data Sheet V3P3A GNDA V3P3SYS V3P3D V3P3D VBAT VBAT VOLT REG GNDD LCD_ONLY SLEEP V2P5 2.5V to logic V3P3D LCD_GEN VLC2 ...
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... Data Sheet IA VA MUX VBIAS IB VB VBAT VREF TEMP VREF_CAL MUX VREF_DIS MUX CROSS CTRL EQU CK32 MUX_ALT CHOP_E MUX_DIV OSC RTCLK (32KHz) XIN (32KHz) XOUT CKTEST/ SEG19 4.9MHz CKOUT_E CK_GEN CK_2X ECK_DIS MPU_DIV MUX_SYNC CKCE <4.9MHz TEST TEST MODE ...
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... Figure 23: Power-Up Timing with V3P3SYS and VBAT Tied Together Rev. 1.2 Transition MISSION 13..14 CK cycles Xtal 2048...4096 CK32 cycles BROWN- MISSION OUT Xtal 14.5 CK32 cycles 4096 CK32 cycles 1024 CK32 cycles 78M6612 Data Sheet 300nA PLL (4.2MHz/MUX_DIV) time 300nA PLL (4.2MHz) time 59 ...
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... If system power is not present, the reset timer duration will be 2 cycles of the crystal clock, at which time the MPU will begin executing in BROWNOUT mode, starting at address 00. Power Fault Circuit: The 78M6612 includes a comparator to monitor system power fault conditions. When the output of the comparator falls (V1<VBIAS), the I/P RAM bits PLL_OK is zeroed and the part switches to BROWNOUT mode if a battery is present ...
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... All configuration bits will be in reset state, and RTC and MPU RAM data will be unknown and must be initialized by the MPU. 2.5 Wake Up Behavior As described above, the 78M6612 will always wake up in mission mode when system power is restored. Additionally, the part will wake up in BROWNOUT mode when a timeout of the wake-up timer occurs. 2.5.1 Wake on Timer If the part is in SLEEP or LCD mode, it can be awakened by the wake-up timer ...
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... Data Sheet 2.7 CE/MPU Communication Figure 26 shows the functional relationship between CE and MPU. The CE is controlled by the MPU via shared registers in the I/O RAM and by registers in the CE DRAM. The CE outputs two interrupt signals to the MPU: CE_BUSY and XFER_BUSY, which are connected to the MPU interrupt service inputs as external interrupts ...
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... Connection of Sensors (CT, Resistive Shunt) Figure 27 and Figure 28 show how resistive dividers, current transformers, and restive shunts are connected to the voltage and current inputs of the 78M6612. Figure 27: Resistive Voltage Divider (Left), Current Transformer (Right) Rev. 1.2 Figure 28: Resistive Shunt 78M6612 Data Sheet ...
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... GAIN _ ADJ In a power and energy measurement unit, the 78M6612 is not the only component contributing to temperature dependency. A whole range of components (e.g. current transformers, resistor dividers, power sources, filter capacitors) will contribute temperature effects. Since the output of the on-chip temperature sensor is accessible to the MPU, temperature- compensation mechanisms with great flexibility are possible ...
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... Rev. 1.2 Measured Frequency [Hz] 32767.98 32768.28 0 32768.38 32768.08 32767.58 Figure 29 -25 0 Figure 30). ⋅ nom 78M6612 Data Sheet Table 45. Deviation from Nominal Frequency [PPM] -0.61 8.545 11.597 2.441 -12.817 shows, even a constant 25 50 T ...
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... MAIN_EDGE_X address. This count is equivalent to twice the line frequency, and can be used to synchronize and/or correct the RTC. 3.5 Connecting 5V Devices All digital input pins of the 78M6612 are compatible with external 5V devices. I/O pins configured as inputs do not require current-limiting resistors when they are connected to external 5V devices. 66 ...
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... DS_6612_001 3.6 Connecting LCDs The 78M6612 has a LCD controller on-chip capable of controlling static or multiplexed LCDs. shows the basic connection for a LCD. 78M6612 The LCD segment pins can be organized in the following groups: 1. Seventeen pins are dedicated LCD segment pins (SEG0 to SEG13, SEG16 to SEG18). ...
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... Data Sheet Table 46: LCD and DIO Pin Assignment by LCD_NUM for the QFN-68 Package SEG in Addition LCD_NUM to SEG0-SEG18 0 None 40-41 3 39-41 4 39-41 5 37, 39-41 6 36-37, 39-41 7 35-37, 39-41 8 34-37, 39-41 9 34-37, 39-41 10 34-37, 39-41 11 31, 34-37, 39-41 30-31, 34-37, 12 39-41 29-31, 34-37, ...
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... SEG18 17 4-11, 14-17, 19 4-11, 14-17, 19 4-11, 14-17 4-11, 14-17 19 4-11, 14-17 20 4-11, 14-16 21 4-11, 14-15 22 4-11 4-11 23 4-11 23 4-11 24 4-10 25 4-9 26 4-8 27 4-7 28 4 None 2 C pins SCL and SDA. 78M6612 Data Sheet Total Number of DIO Pins Including DIO1, DIO2 ...
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... Figure 33. DIO5 connects to both the DI and DO pins of the three-wire device. The CS pin must be connected to a vacant DIO pin of the 78M6612. A pull-up resistor of roughly 10 kΩ to V3P3D (to ensure operation in BROWNOUT mode) should be used for the DI/DO signals, and the CS pin should be pulled down with a resistor to prevent that the 3-wire device is selected on power-up, before the 78M6612 can establish a stable signal for CS ...
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... A voltage divider should be used to establish that safe range when the power and measurement unit is in mission mode (V1 must be lower than 2 all cases in order to keep the hardware watchdog timer enabled). For proper debugging or loading code into the 78M6612 mounted on a PCB necessary to have a provision like the header shown above R1 in jumper on this header pulls V3P3 disabling the hardware watchdog timer. The parallel impedance of R1 and R2 should be approximately kΩ ...
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... For a production unit, the RESET pin should be protected by the external components shown in Figure 37, right side possible to the IC. The RESET pin can also be directly connected to ground. Since the 78M6612 generates its own power-on reset, a reset button or circuitry, as shown in Figure 37, left side, is only required for test units and prototypes. VBAT/ V3P3 ...
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... Figure 38: External Components for the Emulator Interface 3.13 Crystal Oscillator The oscillator of the 78M6612 drives a standard 32.768 kHz watch crystal. The oscillator has been designed specifically to handle these crystals and is compatible with their high impedance and limited power handling capability. The oscillator power dissipation is very low to maximize the lifetime of any battery backup device attached to VBAT ...
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... Data Sheet 4 Firmware Interface 4.1 I/O RAM Map ‘Not Used’ bits are grayed out, contain no memory and are read by the MPU as zero. Reserved bits may be in use and should not be changed. This table lists only the SFR registers that are not generic 8051 SFR registers. Table 48: I/O RAM Map – ...
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... DIO_DIR0[7:4] Reserved Reserved * DIO_2[4:3] DIO_DIR2 DIO_DIR2[4:3] * [5] INT6 INT5 INT4 Reserved IE_FWCOL1 IE_FWCOL0 FLSH_ERASE[7:0] Not Used Not Used FLSH_PGADR[6:0] EEDATA[7:0] EECTRL[7:0] 78M6612 Data Sheet … LCD_SEG19[3:0] LCD_SEG24[3:0] … LCD_SEG38[3:0] LCD_BLKMAP18[3:0] RTM0 RTM1 RTM2 RTM3 PLS_W PLS_I Bit 3 Bit 2 Bit 1 DIO_0[3]* DIO_0[2:1] DIO_DIR0 ...
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... Data Sheet 4.3 I/O RAM Description – Alphabetical Order Bits with a W (write) direction are written by the MPU into configuration RAM. Typically, they are initially stored in Flash memory and copied to the configuration RAM by the MPU. Some of the more frequently programmed bits are mapped to the MPU SFR memory space. The remaining bits are mapped to the address range 0x2xxx. Bits with R (read) direction can be read by the MPU. Columns labeled “ ...
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... See the Interrupts section for details R/W The length of the ADC decimation FIR filter. 1-384 cycles, 0-288 cycles When FIR_LEN=1, the ADC has 2.370370x higher gain. 78M6612 Data Sheet Function Disable EEPROM interface 2-Wire EEPROM interface 3-Wire EEPROM interface Not used 77 ...
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... Data Sheet Name Location FLSH_ERASE[7:0] SFR94[7:0] FLSH_MEEN SFRB2[1] SFRB7[7:1] FLSH_PGADR[6:0] (FPAG) SFRB2[0] FLSH_PWE FOVRIDE 20FD[4] SFRE8[2] IE_FWCOL0 IE_FWCOL1 SFRE8[3] SFRE8[6] IE_PLLRISE IE_PLLFALL SFRE8[7] IE_XFER SFRE8[0] SFRE8[1] IE_RTC IE_WAKE SFRE8[5] 78 Rst Wk Dir Description Flash Erase Initiate FLSH_ERASE is used to initiate either the Flash Mass Erase cycle or the Flash Page Erase cycle ...
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... DIO1 and DIO2 (plus DIO3 on the QFN-68 package) are always available, if not used for UART1. See tables in Application Section Takes the 78M6612 to LCD mode. Ignored if system power is present. The part will awaken when autowake timer times out or when system power returns. 0 – R/W LCD Segment Data. Each word contains information for … ...
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... Data Sheet Name Location MUX_DIV[1:0] 2002[7:6] 2007[1:0] OPT_FDC[1:0] RX1DIS 2008[5] 2008[4] RX1INV TX1E[1,0] 2007[7,6] 2008[0] TX1INV TX1MOD 2008[1] PLL_OK 2003[6] PLS_MAXWI DTH 2080[7:0] [7:0] PLS_INTERVAL 2081[7:0] [7:0] 2004[6] PLS_INV PREBOOT SFRB2[7] 2001[7:6] PRE_SAMPS[1:0] 2015 RTC_SEC[5:0] 2016 RTC_MIN[5:0] 2017 RTC_HR[4:0] 2018 ...
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... Flash memory and CE program RAM. This bit is reset on chip reset and may only be set. Attempts to write zero are ignored Takes the 78M6612 to sleep mode. Ignored if system power is present. The part will wake when the autowake timer times out or when system power returns R/W The number of pre-summer outputs summed in the final summer ...
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... Data Sheet Name Location WAKE_ARM 20A9[7] 20A9[2:0] WAKE_PRD 20A9[3] WAKE_RES SFRE8[7] WD_RST 2002[2] WD_OVF WE 201F[7:0] 82 Rst Wk Dir Description 0 – W Arm the autowake timer. Writing this bit arms the autowake timer and presets it with the values presently in WAKE_PRD and WAKE_RES. The autowake timer is reset and disarmed whenever the MPU is in MISSION mode or BROWNOUT mode ...
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... There must be thirteen 32768 Hz cycles per ADC mux frame (see System Timing Diagram, This means that the product of the number of cycles per frame and the number of conversions per frame Rev. 1.2 , where SAG_THR LSB section). 78M6612 Data Sheet . S is the LSB value LSB Figure 16) ...
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... VAR calculation, sag detection, peak detection, and voltage phase measurement. Refer to the applicable 78M6612 Firmware Description Document. 4.4.6 CE Status Since the CE_BUSY interrupt occurs at 2520.6 Hz desirable to minimize the computation required in the interrupt handler of the MPU ...
Page 85
... SAG_CNT, FREQSEL, EXT_PULSE, I1_SHUNT, I2_SHUNT, PULSE_SLOW, and PULSE_FAST. CE Name Address 0x0E CECONFIG The significance of the bits in CECONFIG is shown in the table below. The CE controls the pulse rate based on W1SUM_X + W2SUM_X (and VAR1SUM_X + VAR2SUM_X). Note: The 78M6612 Demo Code creep function halts pulse generation. CECONFIG Name [bit] [15:8] SAG_CNT [7] – ...
Page 86
... Data Sheet 4.4.7.1 Fundamental Energy Measurement Variables The table below describes each transfer variable for fundamental energy measurement. All variables are signed 32 bit integers. Accumulated variables such as WSUM are internally scaled so they have at least 2x margin before overflow when the integration time is 1 second. Additionally, the hardware will not permit output values to ‘ ...
Page 87
... VMAX * 4.255*10 Default Description Kh = VMAX *IMAX * 47.1132 / (WRATE * N Wh/pulse. The default value results 3.2 Wh/pulse when 2520 samples are taken in each accumulation interval 486 (and VMAX=600, IMAX = 52 6). The maximum value for WRATE is 2 ⋅ ⋅ 78M6612 Data Sheet V (peak ACC 15 – ...
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... Data Sheet 4.4.7.5 CE Calibration Parameters The table below lists the parameters that are typically entered to effect calibration of measurement accuracy. CE Name Default Address 0x08 16384 CAL_IA 0x09 CAL_IB 16384 0x0A CAL_VA 16384 0x0B 16384 CAL_VB 0x0C PHADJ_A 0x0D PHADJ_B 4.4.7.6 Other CE Parameters The table below shows CE parameters used for suppression of noise due to scaling and truncation effects ...
Page 89
... Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GNDA. Rev. 1.2 78M6612 Data Sheet -0 4 4 +0 mA, -0 ...
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... Data Sheet 5.2 Recommended External Components Name From To C1 V3P3A AGND V3P3D DGND C2 CSYS V3P3SYS DGND V2P5 DGND C2P5 XIN XOUT XTAL † CXS XIN AGND † XOUT AGND CXL † Depending on trace capacitance, higher or lower values for CXS and CXL must be used. Capacitance from XIN to GNDD and XOUT to GNDD (combining pin, trace and crystal capacitance) should ...
Page 91
... VIN=0V, ICE_E=1 VIN=V3P3D Condition LOAD LOAD LOAD LOAD SOURCE I =20 mA SINK Condition Vin = VBIAS – 100 mV +100 mV overdrive Condition FIR_LEN=0 FIR_LEN=1 78M6612 Data Sheet Min Typ Max Unit 2 V 0.8 V µA 10 100 µA 10 100 µ 100 µ µA Min Typ Max ...
Page 92
... Data Sheet 5.4.5 92 DS_6612_001 Rev. 1.2 ...
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... I V3P3D Condition Min Reduce V3P3 until V2P5 drops 200 mV RESET=0, iload=0 -3 Condition Min I =0 2.0 LOAD LOAD I =1 mA, LOAD Reduce VBAT until REG_LP_OK=0 78M6612 Data Sheet Typ Max Unit 6.1 7.7 mA +300 nA mA/ 0.5 MHz 9 µA 48 120 µA 65 150 µA 5 ...
Page 94
... Data Sheet PSRR ΔV2P5/ΔVBAT -50 LOAD DS_6612_001 50 mV/V Rev. 1.2 ...
Page 95
... VNOM ( T ) VREF ( -40ºC to +85º ºC (-1 -40 º ºC (-4%) Condition With respect to VLCD With respect to 2*VLC2/3 With respect to VLC2/2 With respect to VLC2/3 With respect to VLC2/2 78M6612 Data Sheet Min Typ Max Unit µ Min Typ Max Unit 1.195 1.197 kΩ ...
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... Data Sheet ADC Converter, V3P3A Referenced =0, VREF_DIS=0, LSB values do not include the 9-bit left shift at CE input. FIR_LEN Parameter Recommended Input Range (Vin-V3P3A) Voltage to Current Crosstalk Vcrosstalk ∠ − ∠ cos( Vin Vcrosstalk Vin THD (First 10 harmonics) 250 mV-pk 20 mV-pk ...
Page 97
... Condition Min Condition Min CKMPU=4.9152 MHz, Using interrupts CKMPU=4.9152 MHz, “bit-banging” DIO4/5 CKMPU=4.9152 MHz Condition Min 5 +100 mv overdrive 10 Condition Min 2000 78M6612 Data Sheet Typ Max Unit Cycles Cycles Cycles 100 ns Cycles Years Years 2 Cycles Typ Max Unit 42 µs ...
Page 98
... Data Sheet 5.5.6 Typical Performance Data 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0.01 Figure 39: Wh Accuracy 120 V/60 Hz and Room Temperature Using a 4 mΩ 50Hz Harmonic Data - Measured at current distortion amplitude of 40% and voltage distortion amplitude of 10%. ...
Page 99
... DS_6612_001 -10 -20 -30 -60 -40 Figure 41: Typical Measurement Accuracy over Temperature Relative to 25°C Rev. 1.2 Relative Accuracy over Temperature - Temperature [°C] 78M6612 Data Sheet 80 100 99 ...
Page 100
... Data Sheet 6 Packaging 6.1 64 LQFP Package 6.1.1 Pinout GNDD 1 E_RXTX/SEG38 2 3 TX1/DIO2 4 TMUXOUT 5 TX0 SEG3 6 V3P3D 7 SEG19/CKTEST 8 V3P3SYS 9 SEG4 10 SEG5 11 SEG37/DIO17 12 COM0 13 14 COM1 15 COM2 16 COM3 100 TERIDIAN 78M6612-IGT Figure 42: 64-Pin LQFP Pinout DS_6612_001 48 RESET 47 V2P5 46 VBAT SEG40/DIO20 43 SEG31/DIO11 42 SEG30/DIO10 ...
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... DS_6612_001 6.1.2 Package Outline (LQFP 64) 11.7 12.3 PIN No. 1 Indicator 0.60 Typ. : Controlling dimensions are in mm. NOTE Rev. 1.2 11.7 12.3 9.8 10.2 0.14 0.50 Typ. 0.28 78M6612 Data Sheet 0.00 0.20 1.40 1.60 101 ...
Page 102
... Data Sheet 6.1.3 Recommended PCB Land Pattern for the LQFP-64 Package x y Recommended PCB Land Pattern Dimensions Symbol Note: The y dimension has been elongated to allow for hand soldering and reworking. Production assembly may allow this dimension to be reduced as long as the G dimension is maintained. ...
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... DIO3 5 TX0 6 SEG3 7 V3P3D 8 CKTEST/SEG19 9 V3P3SYS 10 SEG4 11 SEG5 12 SEG37/DIO17 13 COM0 14 COM1 15 COM2 16 COM3 Rev. 1.2 TERIDIAN 78M6612-IM Figure 43: 68-Pin QFN Pinout 78M6612 Data Sheet RESET 51 V2P5 50 VBAT 49 RX0 48 SEG40/DIO20 47 SEG31/DIO11 46 SEG30/DIO10 45 SEG29/DIO9 44 SEG28/DIO8 43 SEG27/DIO7 42 41 SEG26/DIO6 SEG25/DIO5 40 39 SEG24/DIO4 38 ICE_E 37 SEG18 ...
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... Data Sheet 6.2.2 Package Outline 0.850 Dimensions (in mm): *) Pin length is nominally 0.4mm (min. 0.3 mm, max 0.4 mm). **) Exposed pad is internally connected to GNDD. 104 DS_6612_001 Rev. 1.2 ...
Page 105
... Note 3: The y dimension has been elongated to allow for hand soldering and reworking. Production assembly may allow this dimension to be reduced as long as the G dimension is maintained. Rev. 1.2 Typical Description Dimension Lead pitch 0.4 mm Pad width 0.23 mm Pad length. See Note 3. 0.8 mm See Note 1. 6.3 mm 6.63 mm 7.2 mm 78M6612 Data Sheet 105 ...
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... Data Sheet 7 Pin Descriptions 7.1 Power/Ground Pins Name Type Circuit GNDA P – GNDD P – V3P3A P – V3P3SYS P – V3P3D O 13 VBAT P 12 V2P5 O 10 7.2 Analog Pins Name Type Circuit IA VA VREF O 9 XIN I 8 XOUT Pin types Power Output Input, I/O = Input/Output The circuit number denotes the equivalent circuit, as specified under “ ...
Page 107
... GNDD. To reset the chip, this pin should be pulled high. No external reset circuitry is necessary. Direct connect to ground in normal operation. UART input. If unused, this pin must be terminated to V3P3D or GNDD. UART output. Enables Production Test. Must be grounded in normal operation. 78M6612 Data Sheet 107 ...
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... Data Sheet 8 I/O Equivalent Circuits V3P3D V3P3D 110K Digital CMOS Input Input Pin GNDD Digital Input Equivalent Circuit Type 1: Standard Digital Input or pin configured as DIO Input with Internal Pull-Up V3P3D Digital CMOS Input Input Pin 110K GNDD GNDD Digital Input ...
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... Tape & Reel 32KB Bulk 32KB Tape & Reel Programmed, 32KB Bulk Programmed, 32KB Tape & Reel 78M6612 Data Sheet Package Ordering Number Marking 78M6612-IGT/F 78M6612-IGT 78M6612-IGTR/F 78M6612-IGT 78M6612-IGT/F/P 78M6612-IGT 78M6612-IGT 78M6612-IM/F 78M6612-IM 78M6612-IMR/F 78M6612-IM 78M6612-IM/F/P 78M6612-IM 78M6612-IMR/F/P 78M6612-IM 109 ...
Page 110
... Data Sheet Revision History Revision Date Description 1.0 4/1/2009 First publication. 1.1 5/6/2009 Replaced Miscellaneous editorial corrections. 1.2 6/11/2009 In Section “CE6612_OMU_S2_A01_V1_2”. In Section “I2_SHUNT”. Also changed “W0SUM_X” to “W1SUM_X” and “W1SUM_X” to “W2SUM_X”. In Section “W2SUM_X”. Also changed “VAR0SUM_X” to “VAR1SUM_X” and “ ...
Page 111
... DS_6612_001 Teridian Semiconductor Corp., 6440 Oak Canyon, Suite 100, Irvine, CA 92618 TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com Rev. 1.2 78M6612 Data Sheet 111 ...