NCV8855BMNR2G ON Semiconductor, NCV8855BMNR2G Datasheet - Page 16

• Manufacturer Part Number: NCV8855BMNR2G
• Description: IC BUCK SYNC QUAD 40QFN
• Manufacturer: ON Semiconductor
• Type: Step-Down (Buck)r

Specifications of NCV8855BMNR2G

• Topology: Step-Down (Buck) (2), Linear (LDO) (2)
• Function: Automotive Radio and Instrument Cluster Power Supply
• Number Of Outputs: 4
• Frequency - Switching: 170kHz
• Voltage/current - Output 1: Controller
• Voltage/current - Output 2: Adjustable, 2.5A
• Voltage/current - Output 3: Controller
• W/led Driver: No
• W/supervisor: No
• W/sequencer: Yes
• Voltage - Supply: 9 V ~ 18 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN Exposed Pad
• Voltage - Output: Adjustable
• Voltage - Input: 9 ~ 18 V
• Internal Switch(s): Both
• Synchronous Rectifier: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Power - Output: -
• Other names: NCV8855BMNR2G; NCV8855BMNR2GOSTR

shutdown behavior when VOUT3 is derived from VOUT1
(as shown in Figure 1).
LDO_EN
shutdown during a high battery condition. When VIN
exceeds 18.5 V (typ) the IC will shutdown all outputs. When
V
start up and resume normal operation.
Out−of−Phase Synchronization
switching cycle, which corresponds to 180° phase delay.
Advantages of out−of−phase synchronization are many.
Interleaving the current pulses at the input reduces the input
RMS current. This reduction minimizes the input filter
requirement, allowing the use of smaller components, hence
a more cost effective solution. In addition, since peak current
is reduced, emitted EMI is also reduced.
Synchronizing (SYNC)
achieved by providing a 10 to 90% duty cycle clock to the
SNYC pin. The rising edge of the clock signal will
immediately reset the internal RAMP of SMPS2 and begin
a new pulse for SMPS2. Conversely, the falling edge of the
clock signal will immediately reset the internal RAMP of
SMPS1 and begin a new pulse for SMPS1. The first rising
edge of the external clock signal may cause a momentary
phase diversion between SMPS1 and SMPS2, but will lock
into desired phase on the subsequent falling edge. During
start up, the SYNC pin must not be held at a logic high.
Thermal Warning (HOT_FLG) and Thermal Shutdown
If any of these two exceeds the warning threshold, the
HOT_FLG will assert low. In addition, if thermal monitor 1
(T
switch current limit will fold back to 1.4 A (typ). If
T
latch off while the other device functions will continue to
operate. A HS_EN or SYS_EN toggle will be required to
SYS_EN
VOUT1
VOUT2
VOUT3
VOUT4
Startup and Shutdown Behavior
MON_HSS
8V_IC
5V_IC
IN
In addition to the enable pins, the IC features an automatic
By default, the turn−on of SMPS2 is delayed by half the
Synchronizing the NCV8855 to an external frequency is
There are two thermal sensors in the NCV8855 devices.
MON_HSS
VIN
falls below 17.9 V (typ), the IC will go through a typical
17.9 V
18.5 V
>2.2 V
<0.8 V
4.35 V
4.35 V
>2.2 V
<0.8 V
4.2 V
4.2 V
exceeds its TSD point, the high−side switch will
) exceeds the warning threshold, the high−side
Natural Startup
Figure 19.
Natural Decay
Controlled Soft−Star
http://onsemi.com
16
re−start the high−side switch in the case of a T
event.
entire chip (regardless of the state of T
off, and a SYS_EN toggle will be required to restart.
Overcurrent Protection (SMPS1)
V
each switching cycle, after a short blanking time, the voltage
is sampled across the upper MOSFET and compared to the
threshold set by R
halted. This operation repeats every cycle until the
overcurrent condition is removed.
following equation:
value, the maximum R
minimum value of I
the following relationship should be met:
and I
This will insure that undesirable trigger of the over−current
protection is avoided.
monitoring the feedback voltage is incorporated. If the
output voltage goes below 70% of nominal after start−up,
the part is latched off, requiring SYS_EN to be toggled to
restart the part.
(short circuit protection is not). During soft−start, under
normal conditions, the current limit circuit should not trip.
However, with large output capacitance, the current limit
circuit may determine the output voltage rise time instead of
the soft−start circuit. To ensure that the output voltage is
DS(on)
If thermal monitor 2 (T
Overcurrent protection for SMPS1 is implemented via
If this comparator is tripped, then the pulse is immediately
The over−current limit can be calculated with the
where, I
where IOUT1
To protect in the case of a short circuit event, a comparator
The over current protection circuitry is active upon startup
pk−pk
sensing of the upper MOSFET. At the beginning of
External upper
/2 is the peak ripple current above the dc value.
OCSET
MOSFET
I
LIMIT
I
(MAX)
LIMIT
is 50 mA (typ.). To calculate the R
OCSET
OCSET
w IOUT1
OCSET
+
SN1
27
23
is the maximum dc current allowed,
Figure 20.
.
MON_SW
R
DS(on)
OCSET
must be used. In addition to this,
ILIMIT
R
MAX
DS(on)
(at temperature) and the
) exceeds it TSD point, the
)
I
OCSET
I
MON_HSS
pk−pk
2
50 A
R OCSET
MON_HSS
) will latch
(eq. 1)
(eq. 2)
OCSET
TSD