XRP7740ILB-F Exar Corporation, XRP7740ILB-F Datasheet - Page 21

• Manufacturer Part Number: XRP7740ILB-F
• Description: IC CTRLR PWM/LDO STP-DWN 40TQFN
• Manufacturer: Exar Corporation
• Type: Step-Down (Buck)r

Specifications of XRP7740ILB-F

• Number Of Outputs: 5
• Package / Case: 40-WFQFN Exposed Pad
• Topology: Step-Down (Buck) (4), Linear (1)
• Function: Standby Power and GPIOs
• Frequency - Switching: 1.5MHz
• Voltage/current - Output 1: 0.9 V ~ 5.1 V, 5A
• Voltage/current - Output 2: 0.9 V ~ 5.1 V, 15A
• Voltage/current - Output 3: 0.9 V ~ 5.1 V, 5A
• W/led Driver: No
• W/supervisor: Yes
• W/sequencer: No
• Voltage - Supply: 6.5 V ~ 20 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Current - Output: 5A, 15A
• Voltage - Output: 0.9 ~ 5.1 V
• Voltage - Input: 6.5 ~ 20 V
• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Switching Frequency: 300 KHz to 1500 KHz
• Operating Supply Voltage: 6.5 V to 20 V
• Supply Current: 50 mA
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Output Voltage: 0.9 V to 5.1 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 1016-1352 - EVAL BOARD FOR XRP77401016-1344 - IN-SOCKET PROG BRD VIA USB/GUI
• Power - Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 1016-1353

XRP7740
Quad-Output Digital PWM Buck Controller
REV 1.1.0
Soft-Stop
The SET_PD_FALL_CHx register is a 16 bit register. This register specifies the soft-stop delay and ramp (fall-
time) characteristics for when the chip receives a channel disable indication from the Host to shutdown the
channel.
Bits [15:10] specify the delay after disabling a channel but before starting the shutdown of the channel; where
each bit represents 250us steps. Bits [9:0] specify the fall time of the channel; these 10 bits define the number of
microseconds for each 50mV increment to reach the discharge threshold.
Channel Soft-Stop Sequence
Power Good Flag
The XRP7740 allows the user to set the upper and lower bound for a power good signal per channel. The
SET_PWRG_TARG_MAX_CHx register sets the upper bound, the SET_PWRG_TARG_MIN_CHx register sets
the lower bound. Each register has a 20mV LSB resolution. When the output voltage is within bounds the power
good signal is asserted high. Typically the upper bound should be lower than the over-voltage threshold. In
addition, the power good signal can be delayed by a programmable amount set in the SET_PWRGD_DLY_CHx
register. The power good delay is only set after the soft-start period is finished. If the channel has a pre-charged
condition that falls into the power good region, a power good flag is not set until the soft-start is finished.
EXAR RESERVES THE RIGHT TO MAKE CHANGES TO THIS DATASHEET.
EXAR CONFIDENTIAL, PRELIMINARY & PROPRIETARY. DO NOT DISTRIBUTE OR COPY.
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