DEMOBOARD-U3600BM Atmel, DEMOBOARD-U3600BM Datasheet - Page 10

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DEMOBOARD-U3600BM

Manufacturer Part Number
DEMOBOARD-U3600BM
Description
BOARD DEMO FOR U3600BM
Manufacturer
Atmel
Type
Cordless Phone ICr

Specifications of DEMOBOARD-U3600BM

Contents
Board, Software and Documentation
For Use With/related Products
U3600BM
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Table 2-1.
3. Explanation of Special Register Bit M1CP
10
Address
R15
U3600BM
Address +
Bit
R15B0
R15B1
R15B2
R15B3
R15B4
R15B5
R15B6
R15B7
Detailed Register and Register-bit Description (Continued)
Register Name
E5K
E6K25
E10K
E12K5
E25K
SU3
EOSC
EVCO3
Figure 3-1.
M1CP:
This bit is used to increase or decrease the dynamic range of the first mixer.
0 = the dynamic range of the mixer is large, especially for countries where transmit/ receive fre-
quencies are close together (for example, the US).
If the transmit/receive frequency distance is small and the duplex filters don’t have enough sup-
pression, some transmit signals will be seen on the mixer input and could overdrive the mixer
input. Therefore, the dynamic range can be increased to prevent the transmit signal from over-
driving the mixer.
Mixer overdriving would cause sensitivity reduction and other unwanted effects, for example,
cross-modulation, interference, etc.
When this bit is zero, the mixer current is higher. This has the disadvantage of increasing the
dynamic range.
1 = the dynamic range is low. For example, in France the transmit/receive frequency distance is
large and, therefore, the duplexer can suppress more of the transmit frequency. In this case, this
bit can be set to “1”, with the advantage of saving some unnecessary current.
0 = 140 mV, 1 dB compression point (1 mA more for mixer)
1 = 40 mV, 1 dB compression point
Reg-6 Bit-6 M1CP, PD V
Meaning
Selection phase comparator frequency for PLL3: f
Selection phase comparator frequency for PLL3: f
Selection phase comparator frequency for PLL3: f
Selection phase comparator frequency for PLL3: f
Selection phase comparator frequency for PLL3: f
Speed-up phase comparator for PLL3
0 = disable, 1 = enable crystal oscillator(11.15 MHz)
0 = disable, 1 = enable VCO3 and mixer 1
If V
slowly drops down (depending on the capacitor of
V
To prevent slow dop of V
can be enabled so that the voltage drops faster.
DD
BATA
V
) and this can cause problems.
BATA
PD V
is switched off from V
DD
DD
-bit
-bit
V
DD
DD
T1
, the transistor T1
about 10k
DD
then the voltage
ref3
ref3
ref3
ref3
ref3
= 5 kHz
= 6.25 kHz
= 10 kHz
= 12.5 kHz
= 25 kHz
Country Specific
Yes
Yes
Yes
Yes
Yes
-
-
-
4804A–CT0–03/06

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