ATA556714N-DDB Atmel, ATA556714N-DDB Datasheet - Page 14

• Manufacturer Part Number: ATA556714N-DDB
• Description: IC IDIC R/W 330BIT 75PF
• Manufacturer: Atmel

Specifications of ATA556714N-DDB

• Function: Read/Write
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.11
5. Error Handling
5.1
5.2
14
Programming
Errors During Writing
Errors Before or During Programming
ATA5567
When all necessary information has been received by the ATA5567, programming may proceed.
There is a clock delay between the end of the writing sequence and the start of programming.
Typical programming time is 5.6 ms. This cycle includes a data verification read to grant secure
and correct programming. After programming was executed successfully, the ATA5567 enters
block-read mode transmitting the block just programmed (see
Note:
Several error conditions can be detected to ensure that only valid bits are programmed into the
EEPROM. There are two error types, which lead to two different actions.
The following detectable errors could occur during writing data to the ATA5567:
If any of these erroneous conditions were detected, the ATA5567 enters regular-read mode,
starting with block 1 of the page defined in the command sequence.
If the command sequence was received successfully, the following error could still prevent
programming:
In case of a locked block, programming mode will not be entered. The ATA5567 reverts to
block-read mode, continuously transmitting the currently addressed block.
If the command sequence is validated and the addressed block is not write protected, the new
data will be programmed into the EEPROM memory. The new state of the block write protection
bit (lock bit) will be programmed at the same time accordingly.
Each programming cycle consists of 4 consecutive steps: erase block, erase verification
(data = 0 ), programming, write verification (corresponding data bits = 1).
• Wrong number of field clocks between two gaps (that is, not a valid “1” or “0” pulse stream)
• Password mode is activated and the password does not match the contents of block 7
• The number of bits received in the command sequence is incorrect
• The lock bit of the addressed block is set already
• If a data verification error is detected after an executed data block programming, the tag will
stop modulation (modulation defeat) until a new command is transmitted.
Valid bit counts accepted by the ATA5567 are:
Password write
Standard write
AOR wake up
Direct access with PWD
Direct access
Reset command
Page 0/1 regular-read
This timing and behavior is different from the e555x-family predecessors.
70 bits
38 bits
34 bits
38 bits
6 bits
2 bits
2 bits
(PWD = 1)
(PWD = 0)
(PWD = 1)
(PWD = 1)
(PWD = 0)
Figure 4-8 on page
4874F–RFID–07/08
12).