AD6655BCPZ-150 Analog Devices Inc, AD6655BCPZ-150 Datasheet - Page 49

• Manufacturer Part Number: AD6655BCPZ-150
• Description: IC IF RCVR 14BIT 150MSPS 64LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD6655BCPZ-150

• Function: IF Diversity Receiver
• Frequency: 450MHz
• Rf Type: Cellular, CDMA2000, GSM EDGE, W-CDMA
• Secondary Attributes: 32-Bit Numerically Controlled Oscillator
• Package / Case: 64-VFQFN, CSP Exposed Pad
• Receiving Current: 805mA
• Frequency Range: 450MHz
• Rf Ic Case Style: LFCSP
• No. Of Pins: 64
• Supply Voltage Range: 1.7V To 1.9V
• Operating Temperature Range: -40°C To +85°C
• Frequency Max: 650MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD6655-150EBZ - BOARD EVAL FOR 150MSPS AD6655
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
the SDIO/DCS pin, the SCLK/DFS pin, the SMI SDO/OEB pin,
and the SMI SCLK/PDWN pin serve as standalone CMOS-
compatible control pins. When the device is powered up, it is
assumed that the user intends to use the pins as static control
lines for the duty cycle stabilizer, output data format, output
enable, and power-down feature control. In this mode, the CSB
chip select should be connected to AVDD, which disables the
serial port interface.
Table 27. Mode Selection
Pin
SDIO/DCS
SCLK/DFS
SMI SDO/OEB
SMI SCLK/PDWN
SCLK
SDIO
CSB
DON’T CARE
DON’T CARE
t
S
R/W
External
Voltage
AVDD (default)
AGND
AVDD
AGND (default)
AVDD
AGND (default)
AVDD
AGND (default)
t
DS
W1
W0
t
DH
A12
Configuration
Duty cycle stabilizer
enabled
Duty cycle stabilizer
disabled
Twos complement
enabled
Offset binary enabled
Outputs in high
impedance
Outputs enabled
Chip in power-down or
standby
Normal operation
t
HIGH
A11
t
Figure 81. Serial Port Interface Timing Diagram
LOW
A10
A9
Rev. A | Page 49 of 88
t
CLK
A8
A7
SPI ACCESSIBLE FEATURES
Table 28 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in Application Note AN-877, Interfacing to High Speed ADCs via
SPI (see www.analog.com). The AD6655 part-specific features
are described in the Memory Map Register Description section.
Table 28. Features Accessible Using the SPI
Feature Name
Mode
Clock
Offset
Test I/O
Output Mode
Output Phase
Output Delay
VREF
D5
D4
Description
Allows the user to set either power-down mode
or standby mode
Allows the user to access the DCS via the SPI
Allows the user to digitally adjust the
converter offset
Allows the user to set test modes to have
known data on output bits
Allows the user to set up outputs
Allows the user to set the output clock polarity
Allows the user to vary the DCO delay
Allows the user to set the reference voltage
D3
D2
D1
D0
t
H
DON’T CARE
AD6655
DON’T CARE