RF3854TR7 RFMD, RF3854TR7 Datasheet - Page 14

• Manufacturer Part Number: RF3854TR7
• Description: IC QUADRATURE MOD QUAD-BND 24QFN
• Manufacturer: RFMD

Specifications of RF3854TR7

• Function: Modulator
• Lo Frequency: 800MHz ~ 2GHz
• Rf Frequency: 800MHz ~ 2GHz
• P1db: 7dBm
• Noise Floor: -150dBm/Hz
• Current - Supply: 110mA
• Voltage - Supply: 2.7 V ~ 3.3 V
• Test Frequency: 2.11GHz
• Package / Case: 24-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output Power: -
• Other names: 689-1029-2

RF3854
14 of 26
Pin
10
11
6
7
8
9
Function
MODE D
MODE C
Q SIG N
Q SIG P
GC DEC
VREF
Description
Chip enable control pin. See the Logic Truth table.
CMOS Logic inputs: Logic 0=0V to 0.4V; Logic 1=1.4V to V
Mode control pin. See the Logic Truth table.
CMOS Logic inputs: Logic 0=0V to 0.4V; Logic 1=1.4V to V
Quadrature Q channel negative baseband input port.
Best performance is achieved when the QSIGP and QSIGN are driven dif-
ferentially with a 1.2V common mode DC voltage. The recommended dif-
ferential drive level (V
CDMA modulation and 1.0V
This input should be DC-biased at 1.2V. In sleep mode an internal FET
switch is opened, the input goes high impedance and the modulator is de-
biased.
Phase or amplitude errors between the QSIGP and QSIGN signals will
result in a common-mode signal which may result in an increase in the
even order distortion of the modulation in the output spectrum.
DC offsets between the QSIGP and QSIGN signals will result in increased
carrier leakage. Small DC offsets may be deliberately applied between the
ISIGP/ISIGN and QSIGP/QSIGN inputs to cancel out the LO leakage. The
optimum corrective DC offsets will change with mode, frequency and gain
control.
Common-mode noise on the QSIGP and QSIGN should be kept low as it
may degrade the noise performance of the modulator.
Phase offsets from quadrature between the I and Q baseband signals
results in degraded sideband suppression.
Quadrature Q channel negative baseband input port. See pin 8.
Voltage reference decouple.
External 10nF decoupling capacitor to ground.
The voltage on this pin is typically 1.67V when the chip is enabled. The
voltage is 0V when the chip is powered down.
The purpose of this decoupling capacitor is to filter out low frequency noise
(20MHz) on the gain control lines.
Poor positioning of the VREF decoupling capacitor can cause a degrada-
tion in LO leakage.
A voltage of around 2.5V on this pin indicates that the die flag under the
chip is not grounded and the chip is not biased correctly.
Gain control voltage decouple with an external 1nF decoupling capacitor to
ground.
The voltage on this pin is a function of gain control (GC) voltage when the
chip is enabled. The voltage is 0V when the chip is powered down.
The purpose of this decoupling capacitor is to filter out low frequency noise
(20MHz) on the gain control lines. The size capacitor on the GC DEC line
will effect the settling time response to a step in gain control voltage. A 1nF
capacitor equates to around 200ns settling time and a 0.5nF capacitor
equates to a 100ns settling time. There is a trade-off between settling time
and noise contributions by the gain control circuitry as gain control is
applied.
Poor positioning of the VREF decoupling capacitor can cause a degrada-
tion in LO leakage.
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at ([phone] or [e-mail].
QSIGP
-V
P-P
QSIGN
for GMSK modulation.
) is 1.2V
P-P
for EDGE, 0.8V
CC
CC
P-P
.
.
for W-
Interface Schematic
See pin 6.
See pin 8.
V
CC2
-
+
-
+
4 kΩ
4 kΩ
x1
V
C C 2
Rev A1 DS070313
V
V
CC2
CC2