LTC4402-2EMS Linear Technology, LTC4402-2EMS Datasheet - Page 5

• Manufacturer Part Number: LTC4402-2EMS
• Description: IC CTRLR RF PWR MULTIBAND 10MSOP
• Manufacturer: Linear Technology

Specifications of LTC4402-2EMS

• Rf Type: Cellular, GSM, GPRS, PCS, Wireless Modem, TDMA
• Frequency: 300MHz ~ 2.4GHz
• Features: Dual Output
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIONS
Operation
The LTC4402-1/-2 single/dual band RF power controller
integrates several functions to provide RF power control
over frequencies ranging from 300MHz to 2.4GHz. These
functions include an internally compensated amplifier to
control the RF output power, an autozero section to cancel
internal and external voltage offsets, an RF Schottky diode
peak detector and amplifier to convert the RF feedback
signal to DC, a multiplexer to switch the controller output
to either V
pression and a bandgap reference.
Band Selection
The LTC4402-2 is designed for multiband operation. The
BSEL pin will select output V
V
an 850MHz/900MHz channel and V
channel. BSEL must be established before the part is
enabled. The LTC4402-1 can be used to drive a single RF
channel or dual channel with integral multiplexer.
Control Amplifier
The control amplifier supplies the power control voltage to
the RF power amplifier. A portion (typically – 19dB for low
frequencies and –14dB for high frequencies) of the RF
output voltage is coupled into the RF pin, to close the gain
control loop. When a DAC voltage is applied to PCTL, the
amplifier quickly servos V
detected feedback voltage applied to the RF pin matches
the voltage at PCTL. This feedback loop provides accurate
RF power control. V
6mA load current and 100pF load capacitor.
RF Detector
The internal RF Schottky diode peak detector and ampli-
fier convert the coupled RF feedback voltage to a low
frequency voltage. This voltage is compared to the DAC
voltage at the PCTL pin by the control amplifier to close
the RF power control loop. The RF pin input resistance is
typically 250
300MHz to 2400MHz. The detector demonstrates excel-
lent efficiency and linearity over a wide range of input
power. The Schottky detector is biased at about 60 A and
drives an on-chip peak detector capacitor of 28pF.
PCB
when high. For example, V
PCA
or V
and the frequency range of this pin is
PCB
U
PCA
, a V
or V
INFORMATION
U
PCA/B
PCA
PCB
PCA
or V
PCA
overvoltage clamp, com-
are capable of driving a
when low and output
could be used to drive
W
PCB
PCB
a 1.8GHz/1.9GHz
positive until the
U
Autozero
An autozero system is included to improve power pro-
gramming accuracy over temperature. This section can-
cels internal offsets associated with the Schottky diode
detector and control amplifier. External offsets associated
with the DAC driving the PCTL pin are also cancelled.
Offset drift due to temperature is cancelled between each
burst. The maximum offset allowed at the DAC output is
limited to 400mV. Autozeroing is performed after SHDN
is asserted high. An internal delay of typically 9 s enables
the V
part is enabled, the autozero capacitors are held and the
V
output. The hold droop voltage of typically < 1 V/ms
provides for accurate offset cancellation.
Filter
There is a 270kHz filter included in the PCTL path. This
filter is trimmed at test.
Modes of Operation
Shutdown: The part is in shutdown mode when SHDN is
low. V
supply current is typically 10 A.
Enable: When SHDN is asserted high the part will auto-
matically calibrate out all offsets. This takes about 9 s and
is controlled by an internal delay circuit. After 9 s V
V
user can then apply the ramp signal. The user should wait
at least 11 s after SHDN has been asserted high before
applying the ramp. The DAC should be settled 2 s after
asserting SHDN high.
Hold: When the V
feedback loop is closed and the LTC4402-X servos the
V
RF inputs. When the V
power control feedback loop is opened and the power
control voltage at V
Generally, the V
up ramp has been completed and the desired RF output
power has been achieved. The power control voltage is
then held at a constant voltage during the EDGE modula-
tion time. After the EDGE modulation is completed and
prior to power ramping down, the V
PCA
PCB
PCA
/V
PCA/B
will step up to the starting voltage of 450mV. The
or V
PCA
PCB
output after the autozero has settled. When the
PCB
and V
pins according to the voltages at the PCTL and
pin is connected to the buffer amplifier
HOLD
LTC4402-1/LTC4402-2
PCB
HOLD
PCA
are held at ground and the power
pin is asserted high after the power
HOLD
or V
pin is low, the RF power control
CPB
pin is asserted high, the RF
is held at its present level.
HOLD
pin is set low.
PCA
5
4402f
or