SI4320-J1-FT Silicon Laboratories Inc, SI4320-J1-FT Datasheet - Page 12

• Manufacturer Part Number: SI4320-J1-FT
• Description: IC RCVR FSK 915MHZ 5.4V 16-TSSOP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4320-J1-FT

• Package / Case: 16-TSSOP
• Frequency: 315MHz, 433MHz, 868MHz, and 915MHz
• Sensitivity: -109dBm
• Data Rate - Maximum: 256 kbps
• Modulation Or Protocol: FSK, OOK
• Current - Receiving: 14mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 2.2 V ~ 5.4 V
• Operating Temperature: -40°C ~ 85°C
• Operating Frequency: 315 MHz to 915 MHz
• Operating Supply Voltage: 2.2 V to 5.4 V
• Mounting Style: SMD/SMT
• Supply Current: 3 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Applications: -
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1627-5

Control Commands
Note: In the following tables the POR column shows the default values of the command registers after power-on.
1. Configuration Setting Command
10
11
12
1
2
3
4
5
6
7
8
9
bit
Control Word
Configuration Setting Command
Frequency Setting Command
Receiver Setting Command
Wake-up Timer Command
Low Duty-Cycle Command
Low Battery Detector and Clock Divider
Command
AFC Control Command
Data Filter Command
Data Rate Command
Output and FIFO Command
Reset Mode Command
Status Read Command
15
1
14
b1
0
0
0
1
1
i2
0
0
0
0
1
1
1
1
b0
13
0
1
0
1
0
i1
0
0
1
1
0
0
1
1
Frequency Band [MHz]
12
b1
i0
0
1
0
1
0
1
0
1
11
b0
Bandwidth [kHz]
315
433
868
915
Baseband
reserved
reserved
10
eb
400
340
270
200
134
67
et
9
ex
8
Related Parameters/Functions
Frequency band, low battery detector, wake-up timer,
crystal oscillator load capacitance, baseband filter
bandwidth, clock output
Set the frequency of the local oscillator
Set VDI source, LNA gain, RSSI threshold,
Wake-up time period
Set duty-cycle, enable low duty-cycle mode.
Set LBD threshold voltage and microcontroller clock
division ratio
Set AFC parameters
Set data filter type, clock recovery parameters
Bit rate
Set FIFO IT level, FIFO start control, FIFO enable
and FIFO fill enable
Enable / disable sensitive reset
Read status information
x3
7
x2
6
Bits eb and et control the operation of the low battery detector and
wake-up
corresponding bit is set.
If
When dc bit is set it disables the clock output
x1
5
ex
x3
0
0
0
0
1
1
x0
4
is
timer,
x2
set
0
0
0
0
1
1
i2
3
x1
the
0
0
1
1
1
1
respectively.
i1
2
x0
0
1
0
1
0
1
crystal
i0
1
Crystal Load Capacitance [pF]
is
…
dc
0
They
active
are
Related Control Bits
b1 to b0, eb, et, ex, x3 to
x0, i2 to i0, dc
f11 to f0
d1 to d0, g1 to g0, r2 to
r0, en
r4 to r0, m7 to m0
d6 to d0, en
d2 to d0, t4 to t0
a1 to a0, rl1 to rl0, st, fi,
oe, en
al, ml, s1 to s0, f2 to f0
cs, r6 to r0
f3 to f0, s1 to s0, ff, fe
dr
10.0
15.5
16.0
893Ah
8.5
9.0
9.5
POR
during
enabled
sleep
when the
Si4320
mode.
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