T5760-TGQ Atmel, T5760-TGQ Datasheet
T5760-TGQ
Specifications of T5760-TGQ
Related parts for T5760-TGQ
T5760-TGQ Summary of contents
Page 1
... Low-cost Solution Due to High Integration Level with Minimum External Circuitry Requirements 1. Description The T5760/T5761 is a multi-chip PLL receiver device supplied in an SO20 package. It has been especially developed for the demands of RF low-cost data transmission systems with data rates from 1 kBaud to 10 kBaud in Manchester or Bi-phase code. ...
Page 2
... Figure 1-2. Block Diagram CDEM SENS AVCC AGND DGND DVCC LNAREF LNA_IN LNA LNAGND T5760/T5761 2 FSK/ASK- Dem_out demodulator and data filter Rssi Limiter out RSSI IF Amp. Sensitivity- Polling circuit reduction control logic 4. Order f0 = 950 kHz/ 1 MHz FE LPF fg = 2.2 MHz Standby logic ...
Page 3
... Not connected, connect to GND Crystal oscillator XTAL connection Digital power supply Test pin, during operation at DVCC Bit clock of data stream Digital ground Selects polling or receiving mode; Low: receiving mode, High: polling mode Data output/configuration input T5760/T5761 DATA DGND DATA_CLK TEST 4 DVCC XTAL NC ...
Page 4
... CM (motional capacitance used, an additional XTO pulling of ±30 ppm has to be added. The resulting total LO tolerance of ±120 ppm agrees with the receiving bandwidth specification of the T5760/T5761 if the T5750 has also a total LO tolerance of ±120 ppm. Figure 3-1. The nominal frequency f ...
Page 5
... LNA_IN. The input impedance of that pin is provided in the electrical parameters. The parasitic board inductances and capacitances influence the input matching. The RF receiver T5760/T5761 exhibits its highest sensitivity if the LNA is power matched. This makes the match- ing to an SAW filter as well antenna easier. ...
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... Therefore, CDEM cannot be increased to very high values if self-polling is used. On the other hand CDEM must be large enough to meet the data filter requirements according to the data sig- nal. Recommended values for CDEM are given in the electrical characteristics. T5760/T5761 6 Figure 14-1 on page 29 or GND via a microcontroller. The receiver can be switched from ...
Page 7
... The BR_Range is defined in the OPMODE register (refer to section of the Receiver” on page The T5760/T5761 is designed to operate with data coding where the DC level of the data signal is 50%. This is valid for Manchester and Bi-phase coding. If other modulation schemes are used, the DC level should always remain within the range of V sensitivity may be reduced that condition ...
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... Clk • Timing of the polling circuit including bit check • Timing of the analog and digital signal processing • Timing of the register programming • Frequency of the reset marker • IF filter center frequency (f T5760/T5761 8 Wide Band Receiving Frequency Response 0.0 -10.0 -20.0 -30.0 -40 ...
Page 9
... Soff . This period varies check by Bit-check is given in the electrical charac- Bit-check = I S Son T Bit-check Start_microcontroller ) to be tested. Bit-check Start_microcontroller 24), and the basic clock cycle T T5760/T5761 = 915 MHz is mainly -dependent Clk . Clk , all sig- Startup . The condition of the , T , Sleep Startup ). Thus, T Bit-check ...
Page 10
... It can be set to Sleep mode through an OFF command via Pin DATA or POLLING/_ON. Output level on Pin IC_ACTIVE => high Son OFF command T5760/T5761 Sleep Sleep Table 11-7 on page 24, the highest register value of sleep sets the receiver into a Sleep Sleep ...
Page 11
... the check will be continued Lim_max , the bit check will be terminated and the receiver switches to sleep mode. Valid Time Window for Bit Check Dem_out T5760/T5761 Bit check ok 1/2 Bit 1/2 Bit 1/2 Bit Receiving mode Bit-check ...
Page 12
... CV_Lim reaches Lim_max. This is illustrated in Figure 8-4. Timing Diagram During Bit Check (Lim_min = 14, Lim_max = 24) IC_ACTIVE Bit check Dem_out Bit-check- 0 counter T Start-up Start-up mode T5760/T5761 12 = Lim_min T XClk = (Lim_max – XClk , T and T . The time resolution defining T Lim_max XClk (t ...
Page 13
... T Bit-check Bit-check mode Bit-check resulting in a lower current consumption in polling mode. Bit-check , and the count of the checked bits, N requiring a higher value for the transmitter pre-burst T Bit-check Figure 8-2 on page T5760/T5761 0 T Sleep Sleep mode Lim_max) Bit check failed ( CV_Lim Sleep mode Bit-check is given in the electrical characteristics ...
Page 14
... Data_out (DATA) Figure 8-8. Debouncing of the Demodulator Output Dem_out Data_out (DATA) t DATA_min T5760/T5761 14 Figure 8-7 illustrates how Dem_out is synchronized by the extended . This clock is also used for the bit-check counter. Data can change its state only XClk has elapsed. The edge-to-edge time period t ...
Page 15
... OFF command (see 27). The minimum value of t1 depends on BR_Range. The maximum value for t1 is not elapses. Note that the capacitive load at pin DATA is limited (see Sleep “Data Interface” on page 28). T5760/T5761 t t DATA_min DATA_L_max Receiving mode “Digital Noise Suppression” on page 22 ...
Page 16
... Figure 8-11. Timing Diagram of the OFF Command via Pin POLLING/_ON IC_ACTIVE POLLING/_ON Data_out (DATA) Serial bi-directional data line Figure 8-12. Activating the Receiving Mode via Pin POLLING/_ON IC_ACTIVE POLLING/_ON Data_out (DATA) Serial bi-directional data line T5760/T5761 t10 t7 Bit 1 ("1") (Start bit) ...
Page 17
... Lim_min_2T = (Lim_min + Lim_max) – (Lim_max – Lim_min)/2 Lim_max_2T= (Lim_min + Lim_max) + (Lim_max – Lim_min)/2 after the edge on pin DATA (see Delay Figure 9-2 on page 18 and Figure 9-4 on page T5760/T5761 , the polling mode is active and the sleep time on3 Sleep must be programmed to 31 (per- Sleep Figure 9-1 on page ...
Page 18
... Note that for Bi-phase-coded signals, the data clock is issued at the end of the bit. Figure 9-1. Timing Diagram of the Data Clock Dem_out Data_out (DATA) DATA_CLK Figure 9-2. Data Clock Disappears Because of a Timing Error Dem_out Data_out (DATA) DATA_CLK T5760/T5761 18 Preburst Bit check '1' '1' '1' '1' '1' ...
Page 19
... Data '0' '1' '1' '0' '1' Start bit Receiving mode, data clock control logic active = Delay Delay1 Delay2 (see X 27). When the level of Data_In is equal to the level of . Delay2 “Data Interface” on page T5760/T5761 '0' '0' Delay1 . For the pup Figure 9-5, Figure 9-6 28). 19 ...
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... Figure 10-3 on page 21 Note that if the last period of the data stream is a high period (rising edge to falling edge), a pulse occurs on pin DATA. The length of the pulse depends on the selected baud-rate range. T5760/T5761 20 Timing Characteristic of the Data Clock (Rising Edge on Pin DATA) ...
Page 21
... Lim_max T ee Data stream '1' '1' '1' T Pulse Receiving mode, data clock control logic active Table 11-9 on page T5760/T5761 Bit check ok Preburst Data Digital Noise Receiving mode, Receiving mode, data clock control bit check aktive logic active Bit check ok Preburst Data Receiving mode, ...
Page 22
... Configuration of the Receiver The T5760/T5761 receiver is configured via two 12-bit RAM registers called OPMODE and LIMIT. The registers can be programmed by means of the bidirectional DATA port. If the register contents have changed due to a voltage drop, this condition is indicated by a certain output pat- tern called reset marker (RM) ...
Page 23
... XLim = 8 (default) BR_Range1 1 (application USA/Europe: BR_Range1 = 1.8 kBaud to 3.2 kBaud) XLim = 4 BR_Range2 0 (application USA/Europe: BR_Range2 = 3.2 kBaud to 5.6 kBaud) XLim = 2 BR_Range3 1 (Application USA/Europe: BR_Range3 = 5.6 kBaud to 10 kBaud) XLim = 1 T5760/T5761 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 – – – – Sleep X Sleep2 ...
Page 24
... Table 11-5. Table 11-6. Table 11-7. Sleep4 ... 0 ... Table 11-8. Table 11-9. Noise Suppression T5760/T5761 24 Effect of the Configuration word N N Bit-check BitChk1 BitChk0 Effect of the Configuration Bit Modulation Modulation ASK/_FSK 0 1 Effect of the Configuration Word Sleep Sleep Sleep3 Sleep2 Sleep1 ... ... ...
Page 25
... Lim_max2 Lim_max1 T5760/T5761 Lower Limit Value for Bit Check Lim_min0 (T = Lim_min Lim_min (default 347 µs for f Lim_min 1 BR_Range0 T = 329 µs for f Lim_min BR_Range0 “Data Clock” on page Upper Limit Value for Bit Check Lim_max0 (TLim_max = (Lim_max – (default) (TLim_max = 661 µs for f 1 BR_Range0, TLim_max = 627 µ ...
Page 26
... Conservation of the Register Information The T5760/T5761 implies an integrated power-on reset and brown-out detection circuitry to pro- vide a mechanism to preserve the RAM register information. According to below the threshold voltage V tion registers in that condition. Once V reset period t To indicate that condition, the receiver displays a reset marker (RM) at pin DATA after a reset. ...
Page 27
... Programming frame T5760/ T5761 R pup DATA 0 ... 20 V Input - Interface Serial bi-directional data line and Figure 13-2. T5760/T5761 t9 t8 Bit 14 Bit 15 ("0") ("0") (Poll8) (Stop bit Start-up Sleep Sleep Start-up mode mode Microcontroller I/O Out1 (microcontroller ) 27 ...
Page 28
... Note that the capacitive load at pin DATA is limited. 14. Data Interface The data interface (see be connected via the pull-up resistor R The applicable pull-up resistor R selected BR_range (see Table 14- T5760/T5761 28 : Clk T Clk Figure 13-2 on page pup depends on the load capacity C pup Table 14-1). ...
Page 29
... C13 6 AGND DVCC 10n T5761 10% 7 XTAL LNAREF 9 LNA_IN TEST3 10 TEST2 LNAGND C16 C17 5.6p 18p ±0.1p 5% np0 np0 Toko LL1608-FS4N7S 4.7nH, ±0.3nH EPCOS B3570 5 OUT 6 OUT_GND 7 CASE_GND 8 CASE_GND T5760/T5761 1. C12 10n 15 10% Q1 C11 14 12p 13 6.77617 MHz np0 1. C12 10n 15 10% Q1 ...
Page 30
... T Sleep Figure 9-1 on OPMODE page 18 and register Figure 14-1 on page 29) Start-up time (see BR_Range0 Figure 8-4 on BR_Range1 T Startup page 12 and BR_Range2 Figure 8-5 on BR_Range3 page 13) T5760/T5761 30 Symbol tot stg T amb P in_max Symbol R thJA = 4.5V to 5.5V 868.3 MHz and 868.3 MHz f ...
Page 31
... T5760/T5761 = 915 MHz, unless otherwise specified. 0 Variable Oscillator Typ. Max. Min. Typ. 0.45 0.24 0.14 0. XClk 3.5/f 3/f Sig Sig 6.5/f ...
Page 32
... Programming t2 delay period Synchroni- t3 zation pulse Delay until of the program t4 window starts Programming t5 window Time frame bit Programming t7 pulse T5760/T5761 32 = 4.5V to 5.5V 868.3 MHz and 868.3 MHz f = 915 MHz RF RF 6.77617 MHz Oscillator 7.14063 MHz Oscillator Min. Typ. Max. Min. Typ. ...
Page 33
... LNA/mixer/IF amplifier Required according to I-ETS 300220 With power matching |S11| < – 868.3 MHz At 915 MHz Within the complete image band -3 BER 10 , FSK mode ASK mode T5760/T5761 = 868.3 MHz and f = 915 MHz, unless otherwise specified 915 MHz RF Variable Oscillator Typ. Max. Min. Typ. ...
Page 34
... Sensitivity variation ASK for full operating range including IF filter compared 25° amb S T5760/T5761 34 = 4.5V to 5.5V Test Conditions T5760 T5761 f = 867.3 MHz at 10 MHz osc At ±f XTO XTO pulling, appropriate load capacitance must be connected to XTAL, crystal 6.77617 MHz (EU) XTAL f = 7.14063 MHz (US) ...
Page 35
... BR_Range1 BR_Range2 BR_Range3 BR_Range0 (default) BR_Range1 BR_Range2 BR_Range3 Upper cut-off frequency programmable in 4 ranges via a serial mode word BR_Range0 (default) BR_Range1 BR_Range2 BR_Range3 T5760/T5761 = 868.3 MHz and f = 915 MHz, unless otherwise specified. 0 Symbol Min. Typ. P –103 –106 Ref_FSK –101 P –101 –104 Ref_FSK – ...
Page 36
... IC_ACTIVE output - Saturation voltage Low - Saturation voltage High POLLING/_ON input - Low level input voltage - High level input voltage TEST 4 pin - High level input voltage TEST 1 pin - Low level input voltage T5760/T5761 36 = 4.5V to 5.5V Test Conditions R connected from pin Sens Sense input matched according to ...
Page 37
... Tube, for 915 MHz ISM band SO20 Taped and reeled, for 915 MHz ISM band 12.95 12.70 2.35 0.25 0.10 11. History Put datasheet in a new template Ordering Information on page 37 changed T5760/T5761 9.15 8.65 7.5 7.3 0.25 10.50 10.20 technical drawings according to DIN specifications 37 ...
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