ATA3741P2-TGQY Atmel, ATA3741P2-TGQY Datasheet - Page 13

• Manufacturer Part Number: ATA3741P2-TGQY
• Description: IC UHF ASK/FSK RECEIVER 20SOIC
• Manufacturer: Atmel

Specifications of ATA3741P2-TGQY

• Frequency: 300MHz ~ 450MHz
• Sensitivity: -108dBm
• Data Rate - Maximum: 10 kBaud
• Modulation Or Protocol: ASK, FSK
• Applications: RKE, TPM, Security Systems
• Current - Receiving: 7mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Other names: ATA3741P2-TGQYTR

5.3
5.3.1
4899B–RKE–10/06
Bit-check Mode
Configuring the Bit Check
In bit-check mode, the incoming data stream is examined to distinguish between a valid signal
from a corresponding transmitter and signals due to noise. This is done by subsequent time
frame checks where the distances between 2 signal edges are continuously compared to a pro-
grammable time window. The maximum count of this edge-to-edge test, before the receiver
switches to receiving mode, is also programmable.
Assuming a modulation scheme that contains 2 edges per bit, two time frame checks verify one
bit. This is valid for Manchester, Bi-phase and most other modulation schemes. The maximum
count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable N
register. This implies 0, 6, 12 and 18 edge-to-edge checks respectively. If N
higher value, the receiver is less likely to switch to the receiving mode due to noise. In the pres-
ence of a valid transmitter signal, the bit check takes less time if N
In polling mode, the bit-check time is not dependent on N
example where 3 bits are tested successfully and the data signal is transferred to pin DATA.
Figure 5-4
the edge-to-edge time t
limit T
the bit check will be terminated and the receiver will switch to sleep mode.
Figure 5-4.
For best noise immunity it is recommended to use a low span between T
This is achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst. A
“11111...” or a “10101...” sequence in Manchester or Bi-phase is a good choice in this regard. A
good compromise between receiver sensitivity and susceptibility to noise is a time window of
±25% regarding the expected edge-to-edge time t
ous edge-to-edge time periods, the bit check limits must be programmed according to the
required span.
The bit-check limits are determined by means of the formula below:
T
T
Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register.
Using the above formulas, Lim_min and Lim_max can be determined according to the required
T
minimum edge-to-edge time t
on page
the upper limit is Lim_max = 63.
Lim_min
Lim_max
Lim_min
Lim_max
, T
= Lim_min
= (Lim_max –1)
15. Due to this, the lower limit should be set to Lim_min
Lim_max
shows how the time window for the bit check is defined by two separate time limits. If
, the check will be continued. If t
Valid Time Window for Bit Check
and T
T
XClk
XClk
ee
Dem_out
is in between the lower bit check limit T
. The time resolution when defining T
T
XClk
ee
(t
DATA_L_min
T
T
lim_max
lim_min
t
ee
, t
DATA_H_min
ee
1/f
is smaller than T
Sig
ee
. Using preburst patterns that contain vari-
) is defined in Section
Bitcheck
.
Figure 5-3 on page 12
Lim_min
Lim_min
Lim_min
Bitcheck
10. The maximum value of
and T
or t
and the upper bit check
Bitcheck
is set to a lower value.
ee
Lim_min
Lim_max
“Receiving Mode”
exceeds T
ATA3741
Bitcheck
in the OPMODE
and T
is T
is set to a
shows an
XClk
Lim_max
Lim_max
. The
13
,
.