SI4322-A0-FT Silicon Laboratories Inc, SI4322-A0-FT Datasheet - Page 17
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SI4322-A0-FT
Manufacturer Part Number
SI4322-A0-FT
Description
IC RX FSK UNI 868/915MHZ 16TSSOP
Manufacturer
Silicon Laboratories Inc
Specifications of SI4322-A0-FT
Package / Case
16-TSSOP
Frequency
868MHz, 915MHz
Sensitivity
-104dBm
Data Rate - Maximum
256 kbps
Modulation Or Protocol
FSK
Applications
Remote Control, RKE, Security Systems
Current - Receiving
14mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Features
RSSI Equipped
Voltage - Supply
2.2 V ~ 3.8 V
Operating Frequency
433 MHz to 915 MHz
Operating Supply Voltage
2.2 V to 3.8 V
Mounting Style
SMD/SMT
Supply Current
0.5 mA
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Modulation Type
FSK
Product Depth (mm)
4.4mm
Operating Supply Voltage (typ)
2.5/3.3V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SI4322-A0-FT
Manufacturer:
SILICON
Quantity:
3 500
Part Number:
SI4322-A0-FT
Manufacturer:
SILICONLABS/芯科
Quantity:
20 000
FIFO Buffered Data Read
In this operating mode, incoming data are clocked into a 48 bit FIFO buffer. The receiver starts to fill up the FIFO when the Valid Data
Indicator (VDI) bit and/or the synchron word recognition circuit indicates potentially real incoming data. This prevents the FIFO from
being filled with noise and overloading the external microcontroller.
For further details see the Receiver Setting Command and the Output and FIFO Command.
Polling Mode:
The nFFS signal selects the buffer directly and its content could be clocked out through pin SDO by SCK. Set the FIFO IT level to 1. In
this case, as long as FFIT indicates received bits in the FIFO, the controller may continue to take the bits away. When FFIT goes low,
no more bits need to be taken. An SPI read command is also available.
Interrupt Controlled Mode:
The user can define the FIFO level (the number of received bits) which will generate the nFFIT when exceeded. The status bits report
the changed FIFO status in this case.
FIFO Read Example with FFIT Polling:
During FIFO access the f
Power Saving Modes
The different operating modes of the chip depend on the following control bits:
nFFS**
SDO
nSEL*
SCK
FFIT
FIFO OUT
0
FO+1
SCK
1
FIFO read out
cannot be higher than f
Operating Mode
FO+2
2
Standby
Active
Sleep
Idle
FO+3
3
NOTE:
*nSEL is used to activate SDO
**nFFS is used to select FIFO
FO+4
4
Setting Comand)
(Configuration
ref
/4, where f
eb or et
X
X
1
0
ref
is the crystal oscillator frequency.
(Receiver Setting
Command
en
1
0
0
0
Setting Command)
(Configuration
ex
1
1
0
0
Si4322
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