MRF49XA-I/ST Microchip Technology, MRF49XA-I/ST Datasheet - Page 37

• Manufacturer Part Number: MRF49XA-I/ST
• Description: IC RF TXRX 433/868/915 16-TSSOP
• Manufacturer: Microchip Technology

Specifications of MRF49XA-I/ST

• Package / Case: 16-TSSOP
• Frequency: 433MHz, 868MHz, 915MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FHSS, FSK
• Applications: Home / Industrial Automation, Remote Access, Security Alarms
• Power - Output: 7dbm
• Sensitivity: -110dBm
• Voltage - Supply: 2.2 V ~ 3.8 V
• Current - Receiving: 11mA
• Current - Transmitting: 15mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 1
• Number Of Transmitters: 2
• Wireless Frequency: 433 MHz to 915 MHz
• Output Power: + 7 dBm
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Modulation: FHSS, FSK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 579-MRF49XA-1/ST

REGISTER 2-12:
EQUATION 2-4:
EQUATION 2-5:
EQUATION 2-6:
© 2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-8
bit 7
bit 6-0
Note 1:
DREx (kbps) = 10000/29 x (DRPV<6:0> + 1) x (1 + DRPE x 7)
where:
DRPV<6:0> is the Decimal Value from 0 to 127 and the Prescaler (DRPE) is ‘1’ (if on) or ‘0’ (if off).
DRPV<6:0> = 10000/[29 x (1 + DRPE x 7) x DREx] – 1
where:
DREx is the Expected Data Rate.
• Slow Mode Accuracy (SMA) = ΔDR/DR < 1/(29 x LN)
• Fast Mode Accuracy (FMA) = ΔDR/DR < 3/(29 x LN)
R/W-1
R/W-0
DRPE
where:
LN is the longest number of expected ones or zeros in the data stream.
ΔDR is the difference in the actual data rate versus the set data rate in the transmitter.
DR is the expected data rate set using DRPV<6:0>.
To calculate the expected data rate, use Equation 2-4. To calculate the DRPV<6:0> decimal value for a
given bit rate, use Equation 2-5. If the prescaler is not used, the data rates range from 2.694 kbps to
344.828 kbps. With the prescaler enabled, the data rates range from 337 bps to 43.103 kbps. The Slow
Clock Recovery mode requires more accurate bit timing when setting the data rate. Equation 2-6 is used
to calculate the data rate accuracy for Fast and Slow modes.
CCB<15:8>: Command Code bits
The command code bits (11000110b) are serially sent to the microcontroller to identify the bits to be
written in the DRSREG.
DRPE: Date Rate Prescaler Enable bit
1 = Enables the prescaler to obtain smaller values of expected data rates. The prescaler value when
0 = Disables the prescaler
DRPV<6:0>: Data Rate Parameter Value bits
These bits represent the decimal value of the 7-bit parameter which is used to calculate the expected
data rate.
R/W-1
R/W-0
enabled is approximately 1/8 of the actual data rate.
DRSREG: DATA RATE VALUE SET REGISTER (POR: 0xC623)
r = reserved bit
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-1
R/W-0
R/W-0
Preliminary
CCB<15:8>
DRPV<6:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(1)
R/W-0
R/W-0
(1)
R/W-1
R/W-0
x = Bit is unknown
MRF49XA
R/W-1
R/W-1
DS70590B-page 35
R/W-0
R/W-1
bit 8
bit 0