ATMEGA64RZAV-10MU Atmel, ATMEGA64RZAV-10MU Datasheet - Page 83

MCU ATMEGA644/AT86RF230 44-QFN

ATMEGA64RZAV-10MU

Manufacturer Part Number
ATMEGA64RZAV-10MU
Description
MCU ATMEGA644/AT86RF230 44-QFN
Manufacturer
Atmel
Series
ATMEGAr
Datasheets

Specifications of ATMEGA64RZAV-10MU

Frequency
2.4GHz
Modulation Or Protocol
802.15.4 Zigbee
Power - Output
3dBm
Sensitivity
-101dBm
Voltage - Supply
1.8 V ~ 3.6 V
Data Interface
PCB, Surface Mount
Memory Size
64kB Flash, 2kB EEPROM, 4kB RAM
Antenna Connector
PCB, Surface Mount
Package / Case
44-VFQFN Exposed Pad
Wireless Frequency
2.4 GHz
Interface Type
JTAG, SPI
Output Power
3 dBm
For Use With
ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFP770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Applications
-
Data Rate - Maximum
-
Current - Transmitting
-
Current - Receiving
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
ATmega64
2593N–AVR–07/10
Table 12-14. Overriding Signals for Alternate Functions in PD3:PD0
Note:
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
1. When enabled, the 2-wire Serial Interface enables Slew-Rate controls on the output pins PD0
and PD1. This is not shown in this table. In addition, spike filters are connected between the
AIO outputs shown in the port figure and the digital logic of the TWI module.
PD3/INT1/
PCINT27
0
0
0
0
0
0
INT1 ENABLE
PCINT27 • PCIE3
1
INT1 INPUT
PCINT27 INPUT
PD2/INT0/
PCINT26
PORTD2 • PUD
RXEN1
0
0
0
INT2 ENABLE
PCINT26 • PCIE3
1
INT0 INPUT
PCINT27 INPUT
PD1/TXD0/
PCINT25
TXEN
PORTD1 • PUD
TXEN
SDA_OUT
TWEN
0
INT1 ENABLE
PCINT25 • PCIE3
1
TXD
PCINT25 INPUT
(1)
ATmega644
PD0/RXD0/
PCINT27
RXEN
PORTD0 • PUD
RXEN
SCL_OUT
TWEN
0
INT0 ENABLE
PCINT24 • PCIE3
1
RXD
PCINT24 INPUT
83

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