ADF7020BCPZ Analog Devices Inc, ADF7020BCPZ Datasheet - Page 22

• Manufacturer Part Number: ADF7020BCPZ
• Description: IC TX FSK/ASK ISM BAND 48LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADF7020BCPZ

• Design Resources: Low power, Long Range, ISM Wireless Measuring Node (CN0164)
• Frequency: 431MHz ~ 478MHz and 862MHz ~ 956MHz
• Data Rate - Maximum: 200kbps
• Modulation Or Protocol: ASK, FSK
• Applications: Data Transfer, RKE, Remote Control/Security Systems
• Power - Output: -16dBm ~ 13dBm
• Sensitivity: -119dBm
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Receiving: 19mA
• Current - Transmitting: 26.8mA @ 10dBm
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LFCSP
• Data Rate: 200Kbps
• Supply Voltage Range: 2.3V To 3.6V
• Logic Case Style: LFCSP
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +85°C
• Msl: MSL 1 - Unlimited
• Termination Type: SMD
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 7mm
• Product Length (mm): 7mm
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF7020DBZ3 - BOARD EVAL ADF7020 433-445MHZEVAL-ADF7020DBZ2 - BOARD EVAL ADF7020 862-870MHZEVAL-ADF7020DBZ1 - BOARD EVAL ADF7020 902-928MHZ
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant

ADF7020
Postdemodulator Filter
A second-order, digital low-pass filter removes excess noise from
the demodulated bit stream at the output of the discriminator.
The bandwidth of this postdemodulator filter is programmable
and must be optimized for the user’s data rate. If the bandwidth
is set too narrow, performance is degraded due to intersymbol
interference (ISI). If the bandwidth is set too wide, excess noise
degrades the receiver’s performance. Typically, the 3 dB bandwidth
of this filter is set at approximately 0.75 times the user’s data rate,
using Bits R4_DB[6:15].
Bit Slicer
The received data is recovered by the threshold detecting the
output of the postdemodulator low-pass filter. In the correlator/
demodulator, the binary output signal levels of the frequency
discriminator are always centered on 0. Therefore, the slicer
threshold level can be fixed at 0, and the demodulator perform-
ance is independent of the run-length constraints of the transmit
data bit stream. This results in robust data recovery, which does
not suffer from the classic baseline wander problems that exist in
the more traditional FSK demodulators.
Frequency errors are removed by an internal AFC loop that
measures the average IF frequency at the limiter output and
applies a frequency correction value to the fractional-N
synthesizer. This loop should be activated when the frequency
errors are greater than approximately 40% of the transmit
frequency deviation (see the AFC section).
Data Synchronizer
An oversampled digital PLL is used to resynchronize the
received bit stream to a local clock. The oversampled clock rate
of the PLL (CDR_CLK) must be set at 32 times the data rate.
See the Register 3—Receiver Clock Register Comments section
for a definition of how to program. The clock recovery PLL can
accommodate frequency errors of up to ±2%.
FSK Correlator Register Settings
To enable the FSK correlator/demodulator, Bits R4_DB[5:4] should
be set to 01. To achieve best performance, the bandwidth of the
FSK correlator must be optimized for the specific deviation
frequency that is used by the FSK transmitter.
LIMITERS
Q
I
R6_DB[4:13]
FREQUENCY CORRELATOR
Figure 30. FSK Correlator/Demodulator Block Diagram
IF –
f
DEV
R6_DB[14]
IF
IF +
f
DEV
0
SLICER
R3_DB[8:15]
RxDATA
RxCLK
Rev. B | Page 22 of 48
The discriminator BW is controlled in Register 6 by
Bit R6_DB[4:13] and is defined as
where:
DEMOD_CLK is as defined in the Register 3—Receiver Clock
Register section, second comment.
K = Round(200 × 10
To optimize the coefficients of the FSK correlator, two addi-
tional bits, R6_DB14 and R6_DB29, must be assigned. The
value of these bits depends on whether K (as defined above) is
odd or even. These bits are assigned according to Table 7 and
Table 8.
Table 7. When K Is Even
K
Even
Even
Table 8. When K Is Odd
K
Odd
Odd
Postdemodulator Bandwidth Register Settings
The 3 dB bandwidth of the postdemodulator filter is controlled
by Bits R4_DB[6:15] and is given by
where f
demodulator filter. This should typically be set to 0.75 times the
data rate (DR).
Some sample settings for the FSK correlator/demodulator are
Therefore,
and
Postdemod_BW_Setting
DEMOD_CLK = 5 MHz
DR = 9.6 kbps
f
f
Postdemod_BW_Setting = 2
Postdemod_BW_Setting = Round (9.26) = 9
K = Round (200 kHz)/20 kHz) = 10
Discriminator_BW = (5 MHz × 10)/(800 × 10
(rounded to the nearest integer)
Discrimina
DEV
CUTOFF
CUTOFF
= 20 kHz
= 0.75 × 9.6 × 10
i s the target 3 dB bandwidth in Hz of the post-
tor
K/2
Even
Odd
(K + 1)/2
Even
Odd
_
3
BW
/FSK Deviation)
=
DEMOD
3
=
Hz
2
11
DEMOD
10
800
R6_DB14
0
0
R6_DB14
1
1
π 7.2 × 10
×
π 2
_
×
CLK
10
×
3
f
_
CUTOFF
CLK
×
3
Hz/(5 MHz)
K
3
R6_DB29
0
1
R6_DB29
0
1
) = 62.5 = 63