ADF7020-1BCPZ Analog Devices Inc, ADF7020-1BCPZ Datasheet - Page 22

• Manufacturer Part Number: ADF7020-1BCPZ
• Description: IC TX FSK/ASK ISM BAND 48LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADF7020-1BCPZ

• Design Resources: Low power, Long Range, ISM Wireless Measuring Node (CN0164)
• Frequency: 431MHz ~ 478MHz and 862MHz ~ 956MHz
• Data Rate - Maximum: 200kbps
• Modulation Or Protocol: ASK, FSK
• Applications: Data Transfer, RKE, Remote Control/Security Systems
• Power - Output: -16dBm ~ 13dBm
• Sensitivity: -119dBm
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Receiving: 17.6mA
• Current - Transmitting: 21mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LFCSP
• Receiving Current: 20.1mA
• Transmitting Current: 13mA
• Data Rate: 200Kbps
• Frequency Range: 135MHz To 650MHz
• Modulation Type: ASK, FSK, GFSK, GOOK, OOK
• Rf Ic Case Style: LFCSP
• No. Of Pins: 48
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 7mm
• Product Length (mm): 7mm
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF7020-1DBZ8 - BOARD EVAL ADF7020-1 128-142MHZEVAL-ADF7020-1DBZ7 - BOARD EVAL ADF7020-1 310-340MHZEVAL-ADF7020-1DBZ6 - BOARD EVAL ADF7020-1 470-510MHZEVAL-ADF7020-1DBZ4 - BOARD EVAL ADF7020-1 405-435MHZEVAL-ADF7020-1DBZ5 - BOARD EVAL ADF7020-2 ADJ FREQ
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant

ADF7020-1
Postdemodulator Filter
A second-order digital low-pass filter removes excess noise from
the demodulated bit stream at the output of the discriminator.
The bandwidth of this postdemodulator filter is programmable
and must be optimized for the user’s data rate. If the bandwidth
is set too narrow, performance is degraded due to intersymbol
interference (ISI). If the bandwidth is set too wide, excess noise
degrades the receiver’s performance. Typically, the 3 dB bandwidth
of this filter is set at approximately 0.75 times the user’s data
rate, using Bits R4_DB (6:15).
Bit Slicer
The received data is recovered by the threshold detecting the
output of the postdemodulator low-pass filter. In the correlator/
demodulator, the binary output signal levels of the frequency
discriminator are always centered on zero. Therefore, the slicer
threshold level can be fixed at zero, and the demodulator
performance is independent of the run-length constraints of the
transmit data bit stream. This results in robust data recovery,
which does not suffer from the classic baseline wander prob-
lems that exist in the more traditional FSK demodulators.
Frequency errors are removed by an internal AFC loop that
measures the average IF frequency at the limiter output and
applies a frequency correction value to the fractional-N
synthesizer. This loop should be activated when the frequency
errors are greater than approximately 40% of the transmit
frequency deviation (see the AFC Section).
Data Synchronizer
An oversampled digital PLL is used to resynchronize the received
bit stream to a local clock. The oversampled clock rate of the
PLL (CDR_CLK) must be set at 32 times the data rate. See the
notes for the Register 3—Receiver Clock Register section for a
definition of how to program the various on-chip clocks. The clock
recovery PLL can accommodate frequency errors of up to ±2%.
FSK Correlator Register Settings
To enable the FSK correlator/demodulator, Bits R4_DB (5:4)
should be set to [01]. To achieve best performance, the bandwidth
of the FSK correlator must be optimized for the specific deviation
frequency that is used by the FSK transmitter.
The discriminator BW is controlled in Register 6 by R6_DB
(4:13) and is defined as
LIMITERS
Q
I
Discrimina
FREQUENCY CORRELATOR
DB(4:13)
Figure 31. FSK Correlator/Demodulator Block Diagram
IF – F
DEV
tor
DB(14)
IF
_
IF + F
BW
DEV
=
(
DEMOD
_
CLK
0
SLICER
×
K
DB(8:15)
)
/(
800
Rx DATA
Rx CLK
×
10
3
Rev. 0 | Page 22 of 48
)
where:
DEMOD_CLK is as defined in the Register 3—Receiver Clock
Register section, Note 2.
K = round(200e3/FSK deviation)
To optimize the coefficients of the FSK correlator, two
additional bits, R6_DB14 and R6_DB29, must be assigned.
The value of these bits depends on whether K (as defined
above) is odd or even. These bits are assigned according to the
conditions listed in Table 8 and Table 9.
Table 8. When K Is Even
K
Even
Even
Table 9. When K Is Odd
K
Odd
Odd
Postdemodulator Bandwidth Register Settings
The 3 dB bandwidth of the postdemodulator filter is controlled
by Bits R4_ DB (6:15) and is given by
where F
demodulator filter. This should typically be set to 0.75 times the
data rate (DR).
Some sample settings for the FSK correlator/demodulator are
Therefore
and
Table 10. Register Settings
Setting Name
Post_Demod_BW
Discriminator_BW
Dot Product
Rx Data Invert
DEMOD_CLK = 5 MHz
DR = 9.6 kbps
F
F
Post_Demod_BW = 2
Post_Demod_BW = Round(9.26) = 9
K = Round(200 kHz)/20 kHz) = 10
Discriminator_BW = (5 MHz × 10)/(800 × 10
63 (rounded to nearest integer)
Post
DEV
CUTOFF
CUTOFF
= 20 kHz
_
Demod
= 0.75 × 9.6 × 10
is the target 3 dB bandwidth in hertz of the post-
K/2
Even
Odd
(K + 1)/2
Even
Odd
_
BW
Register Address
R4_DB (6:15)
R6_DB (4:13)
R6_DB14
R6_DB29
_
11
Setting
π 7.2 × 10
3
Hz
R6_DB14
0
0
R6_DB14
1
1
=
2
3
DEMOD
10
Hz/(5 MHz)
×
π 2
Value
0x09
0x3F
0
1
×
F
_
CUTOFF
CLK
3
R6_DB29
0
1
R6_DB29
0
1
) = 62.5 =