ATMEGA256RZAV-8MU Atmel, ATMEGA256RZAV-8MU Datasheet - Page 129

MCU ATMEGA2561/AT86RF230 64-QFN

ATMEGA256RZAV-8MU

Manufacturer Part Number
ATMEGA256RZAV-8MU
Description
MCU ATMEGA2561/AT86RF230 64-QFN
Manufacturer
Atmel
Series
ATMEGAr
Datasheets

Specifications of ATMEGA256RZAV-8MU

Frequency
2.4GHz
Modulation Or Protocol
802.15.4 Zigbee
Applications
ISM, ZigBee™
Power - Output
3dBm
Sensitivity
-101dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
15.5mA
Current - Transmitting
16.5mA
Data Interface
PCB, Surface Mount
Memory Size
256kB Flash, 4kB EEPROM, 8kB RAM
Antenna Connector
PCB, Surface Mount
Package / Case
64-QFN
Wireless Frequency
2.4 GHz
Interface Type
JTAG, SPI
Output Power
3 dBm
For Use With
ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Data Rate - Maximum
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
ATmega256

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA256RZAV-8MU
Manufacturer:
Atmel
Quantity:
135
15.9
15.9.1
2549M–AVR–09/10
Register Description
TCCR0A – Timer/Counter Control Register A
• Bits 7:6 – COM0A1:0: Compare Match Output A Mode
These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0
bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin
must be set in order to enable the output driver.
When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the
WGM02:0 bit setting.
are set to a normal or CTC mode (non-PWM).
Table 15-2.
Table 15-3
mode.
Table 15-3.
Note:
Table 15-4 on page 130
to phase correct PWM mode.
Bit
0x24 (0x44)
Read/Write
Initial Value
COM0A1
COM0A1
0
0
1
1
0
0
1
1
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at BOTTOM. See
page 124
shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM
Compare Output Mode, non-PWM Mode
Compare Output Mode, Fast PWM Mode
COM0A1
R/W
COM0A0
COM0A0
7
0
for more details.
0
1
0
1
0
1
0
1
Table 15-2
COM0A0
shows the COM0A1:0 bit functionality when the WGM02:0 bits are set
R/W
6
0
ATmega640/1280/1281/2560/2561
shows the COM0A1:0 bit functionality when the WGM02:0 bits
COM0B1
R/W
WGM02 = 0: Normal Port Operation, OC0A Disconnected.
5
0
Clear OC0A on Compare Match, set OC0A at BOTTOM
Set OC0A on Compare Match, clear OC0A at BOTTOM
WGM02 = 1: Toggle OC0A on Compare Match.
Normal port operation, OC0A disconnected.
Normal port operation, OC0A disconnected.
COM0B0
R/W
4
0
Toggle OC0A on Compare Match.
Clear OC0A on Compare Match.
Set OC0A on Compare Match.
(non-inverting mode).
R
(inverting mode).
3
0
(1)
Description
Description
R
2
0
WGM01
R/W
1
0
“Fast PWM Mode” on
WGM00
R/W
0
0
TCCR0A
129

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