SI4421-A1-FT Silicon Laboratories Inc, SI4421-A1-FT Datasheet - Page 21

• Manufacturer Part Number: SI4421-A1-FT
• Description: IC TXRX FSK 915MHZ 3.8V 16-TSSOP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4421-A1-FT

• Package / Case: 16-TSSOP
• Frequency: 433MHz, 868MHz, 915MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK
• Power - Output: 7dbm
• Sensitivity: -110dBm
• Voltage - Supply: 2.2 V ~ 3.6 V
• Current - Receiving: 15mA
• Current - Transmitting: 28mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 2
• Number Of Transmitters: 2
• Wireless Frequency: 433 MHz to 915 MHz
• Interface Type: SPI
• Output Power: 5 dBm to 7 dBm
• Operating Supply Voltage: 2.2 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 25 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1631-5

Bit 1 (ff):
Bit 0 (dr): Disables the highly sensitive RESET mode.
Note: To restart the synchron pattern recognition, bit 1 (ef, FIFO fill enable) should be cleared and set.
8. Synchron Pattern Command
The Byte0 of the synchron pattern (see FIFO and Reset Mode command, page 20) can be reprogrammed by B <b7:b0>.
9. Receiver FIFO Read Command
With this command, the controller can read 8 bits from the receiver FIFO. Bit 6 (ef) must be set in Configuration Setting Command
(page 15).
Note: During FIFO access f
10. AFC Command
Bit 7-6 (a1 to a0):
Bit
Bit
Bit
clock signal is not 50 % the shorter period of the clock pulse width should be at least 2/f
15
15
1
1
15
1
FIFO fill will be enabled after synchron pattern reception. The FIFO fill stops when this bit is cleared.
14
14
1
0
14
1
13
13
0
1
13
0
Automatic operation mode selector:
dr
0
1
a1
0
0
1
1
SCK
12
12
0
1
12
0
cannot be higher than f
a0
0
1
0
1
Non-sensitive reset
11
11
1
0
Sensitive reset
11
0
Reset mode
10
10
1
0
10
1
Keep the f
9
1
9
0
9
0
Auto mode off (Strobe is controlled by microcontroller)
Keep the f
offset
8
0
8
0
8
0
ref
value independently from the state of the VDI signal
Runs only once after each power-up
/4, where f
b7
7
7
0
a1
7
V
offset
dd
below 1.6V, V
Operation mode
b6
only during receiving (VDI=high)
6
6
0
a0
6
ref
is the crystal oscillator frequency. When the duty-cycle of the
Reset triggered when
b5
5
5
rl1
0
5
V
dd
dd
below 250mV
b4
rl0
4
4
0
4
glitch greater than 600mV
b3
3
3
0
st
3
b2
2
2
0
2
fi
ref
b1
oe
.
1
1
0
1
b0
en
0
0
0
0
C4F7h
CED4h
POR
B000h
POR
POR
Si4421
21