ATA5423-PLSW Atmel, ATA5423-PLSW Datasheet - Page 88
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ATA5423-PLSW
Manufacturer Part Number
ATA5423-PLSW
Description
IC TXRX ASK/FSK 315MHZ 48QFN
Manufacturer
Atmel
Specifications of ATA5423-PLSW
Frequency
315MHz
Data Rate - Maximum
20kbps
Modulation Or Protocol
ASK, FSK
Applications
Alarm, ISM, Telemetry
Power - Output
5dBm
Sensitivity
-112.5dBm
Voltage - Supply
2.4 V ~ 3.6 V or 4.4 V ~ 6.6 V
Current - Receiving
10.5mA
Current - Transmitting
10mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Memory Size
-
14. Electrical Characteristics: 2 Li Battery Application (6V) (Continued)
All parameters refer to GND and are valid for T
f
88
RF
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
10.12
10.13
10.14
10.15
10.16
No.
= 315 MHz/345 MHz/433.92 MHz/868.3 MHz/915 MHz unless otherwise specified
1. The voltage of VAUX may rise up to 2 V. The current I
Parameters
Current during
T
Current in
RX polling mode on
on pin VS2
Supply current
RX polling mode
Current in TX mode
on pin VS2
Supply current
TX mode
ATA5423/ATA5425/ATA5428/ATA5429
Startup_PLL
on pin VS2
Test Conditions
I
CLK enabled
V
CLK disabled
V
V
I
P
315 MHz/5 dBm
315 MHz/10 dBm
345 MHz/5 dBm
345 MHz/10 dBm
433.92 MHz/5 dBm
433.92 MHz/10 dBm
868.3 MHz/5 dBm
868.3 MHz/10 dBm
915 MHz/5 dBm
915 MHz/10 dBm
CLK enabled
V
CLK disabled
V
VSOUT
VSOUT
out
VSOUT
VSOUT
VSOUT
VSOUT
VSOUT
I
P
= 5 dBm/10 dBm
=
= 0
= 0
I
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -
enabled
enabled
disabled
enabled
enabled
IDLE_VS2
amb
= 25°C, V
T
SLEEP
VS2
22, 27
17, 19
22, 27
Pin
17,
17,
+
17
= 6.0V. Application according to
I
T
Startup_PLL_VS2
Sleep
VAUX
I
+
Startup_PLL_VS2
may not exceed 100 µA.
T
Symbol
I
Startup_PLL
TX_VS2
I
I
S_Poll
S_TX
T
Startup_PLL
+
T
Startup_Sig_Proc
Min.
+
I
Figure 2-3 on page 9
RX_VS2
I
S_TX
I
Typ.
10.7
16.2
10.8
16.3
10.9
16.3
11.6
17.8
12.3
20.0
S_Poll
9.1
I
S_TX
+
= I
I
S_Poll
T
TX_VS2
= I
Bitcheck
= I
I
T
S_Poll
P
Startup_Sig_Proc
TX_VS2
Max.
= I
+ I
13.9
21.0
14.0
21.2
14.0
21.0
15.0
23.0
16.0
26.0
12
+ I
P
VSINT
= I
+ I
VSINT
P
+ I
EXT
+ I
EXT
Unit
+ I
mA
mA
4841D–WIRE–10/07
EXT
EXT
+
T
Bitcheck
Type*
C
B