SI4010-C2-GS Silicon Laboratories Inc, SI4010-C2-GS Datasheet - Page 48

• Manufacturer Part Number: SI4010-C2-GS
• Description: IC TX 27-960MHZ FSK 3.6V 14SOIC
• Manufacturer: Silicon Laboratories Inc
• Series: EZRadio®r
• Type: Crystalless SoC RF Transmitterr

Specifications of SI4010-C2-GS

• Package / Case: 14-SOIC (0.154", 3.90mm Width)
• Mfg Application Notes: SI4010 Calculator Spreadsheet AppNote
• Frequency: 27MHz ~ 960MHz
• Applications: Garage Openers, RKE, Security Alarms
• Modulation Or Protocol: FSK, OOK
• Data Rate - Maximum: 100 kBaud
• Power - Output: 10dBm
• Current - Transmitting: 19.8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Memory Size: 4kB RAM
• Features: 8051 MCU Core, Crystal-less Operation
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Operating Frequency: 27 MHz to 960 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V to 3.6 V
• Supply Current: 14.2 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1996-5

Si4010-C2
SFR Definition 15.2. SYSGEN
SFR Address = 0xBE
48
Name SYSGEN_
Reset
2:0
Bit
Type
7
6
5
4
3
Bit
PWR_1ST_
SYSGEN_
SYSGEN_
Reserved
TICKCLR
DIV[2:0]
PORT_
DOWN
SHUT-
HOLD
Name
RTC_
TIME
DOWN
SHUT-
R/W
7
0
System General Shutdown.
Setting this bit causes shutdown of MCU and most analog. Recovery from this is via 
falling edge on any GPIO, which results in a power up and a power on reset. This is
THE bit that shuts down the power to nearly everything.
0: Normal operation
1: Shutdown. Do not use this bit directly. It is recommended to use the
vSys_Shutdown() API call.
Read as 0. Write has no effect.
Initial Powerup Indicator.
Read only register. It will get set when power up was caused by a battery insertion.
Real Time Clock Clear.
0: Normal operation
1: Clears the real time clock 5.12us counter.
Port Hold.
This bit needs to be set before shutting down, it delays any button pushes that occur
between this bit setting and shutdown until the chip completes shutdown, to ensure
the shutdown process cannot be interrupted.
0: Normal operation
1: Holds GPIO port values until shutdown is complete
System Clock Generator Divider.
System clock divider control to generate the system clock.
000: 24 MHz; div = 1
001: 12 MHz; div = 2
010: 6.0 MHz; div = 4
011: 3.0 MHz; div = 8
100: 1.5 MHz; div = 16
101: 0.75 MHz; div = 32
110: 0.375 MHz; div = 64
111: 0.1875 MHz; div = 128
Re-served PWR_1ST
R
6
0
_TIME
—
R
5
TICKCLR
RTC_
Rev. 1.0
W
4
0
Function
PORT_
HOLD
R/W
3
0
2
0
SYSGEN_DIV[2:0]
R/W
1
0
0
0