RFPIC12F675HT-I/SS Microchip Technology, RFPIC12F675HT-I/SS Datasheet - Page 15
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RFPIC12F675HT-I/SS
Manufacturer Part Number
RFPIC12F675HT-I/SS
Description
IC MCU 1KX14 RF FSK/ASK 20SSOP
Manufacturer
Microchip Technology
Series
PIC®r
Specifications of RFPIC12F675HT-I/SS
Frequency
850MHz ~ 950MHz
Applications
RKE, Security Systems
Modulation Or Protocol
ASK, FSK
Data Rate - Maximum
40 kbps
Power - Output
10dBm
Current - Transmitting
14mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Memory Size
1024 x 14 words Flash, 128 x 8 Byte EEPROM, 64 x 8 Byte SRAM
Voltage - Supply
2V ~ 5.5V
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SSOP
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
1024 B
Data Ram Size
64 B
Interface Type
USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
4 bit
For Use With
XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC124002 - MOD SKT PROMATEII 18SOIC/20SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Details
Other names
RFPIC12F675HT-ISS
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
RFPIC12F675HT-I/SS
Manufacturer:
MICROCHIP
Quantity:
12 000
2.2.2.5
The PIR1 register contains the interrupt flag bits, as
shown in Register 2-5.
REGISTER 2-5:
2003 Microchip Technology Inc.
bit 7
bit 6
bit 5-4
bit 3
bit 2-1
bit 0
PIR1 Register
PIR1 — PERIPHERAL INTERRUPT REGISTER 1 (ADDRESS: 0Ch)
bit 7
EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation has not completed or has not been started
ADIF: A/D Converter Interrupt Flag bit
1 = The A/D conversion is complete (must be cleared in software)
0 = The A/D conversion is not complete
Unimplemented: Read as ‘0’
CMIF: Comparator Interrupt Flag bit
1 = Comparator input has changed (must be cleared in software)
0 = Comparator input has not changed
Unimplemented: Read as ‘0’
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Legend:
R = Readable bit
- n = Value at POR
R/W-0
EEIF
R/W-0
ADIF
U-0
Preliminary
—
W = Writable bit
’1’ = Bit is set
U-0
—
Note:
R/W-0
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
CMIF
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
rfPIC12F675
U-0
—
x = Bit is unknown
U-0
—
DS70091A-page 13
TMR1IF
R/W-0
bit 0