T48C862M-R4-TNQ Atmel, T48C862M-R4-TNQ Datasheet - Page 46

• Manufacturer Part Number: T48C862M-R4-TNQ
• Description: IC MON TIRE PRESS 433MHZ 24-SOIC
• Manufacturer: Atmel

Specifications of T48C862M-R4-TNQ

• Frequency: 433MHz
• Modulation Or Protocol: FM, FSK
• Data Rate - Maximum: 32 kBaud
• Power - Output: 10dBm
• Current - Transmitting: 9.5mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Memory Size: 1KB EEPROM, 1KB RAM
• Voltage - Supply: 2 V ~ 4 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 24-SOIC (0.200", 5.30mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Applications: -

Mode 3/4: 8-bit Compare
Counter and 4-bit
Programmable Prescaler
Timer 2 Output Modes
46
T48C862-R4 [Preliminary]
Figure 39. 4-/8-bit Compare Counter
In these modes the 4-bit and the 8-bit counter stages work independently as a 4-bit
prescaler and an 8-bit timer with an 2-bit prescaler or as a duty cycle generator. Only in
the mode 3 and mode 4, can the 8-bit counter be supplied via the external clock input
(T2I) which is selected via the P4CR register. The 4-bit prescaler is started via activating
of mode 3 and stopped and reset in mode 4. Changing mode 3 and 4 has no effect for
the 8-bit timer stage. The 4-bit stage can be used as prescaler for Timer 3, the SSI or to
generate the stop signal for modulator 2 and modulator 3.
The signal at the timer output is generated via modulator 2. In the toggle mode, the com-
pare match event toggles the output T2O. For high resolution duty cycle modulation 8
bits or 12 bits can be used to toggle the output. In the duty cycle burst modulator modes
the DCG output is connected to T2O and switched on and off either by the toggle flip-
flop output or the serial data line of the SSI. Modulator 2 also has two modes to output
the content of the serial interface as Biphase or Manchester code.
The modulator output stage can be configured by the output control bits in the T2M2
register. The modulator is started with the start of the shift register (SIR = 0) and
stopped either by carrying out a shift register stop (SIR = 1) or compare match event of
stage 1 (CM1) of Timer 2. For this task, Timer 2 mode 3 must be used and the prescaler
has to be supplied with the internal shift clock (SCL).
Figure 40. Timer 2 Modulator Output Stage
T2I
SYSCL
T1OUT
SYSCL
TOG3
CONTROL
SCL
P4CR
SSI
T2CS1, 0
P41M2, 1
MUX
DCGO
SO
TOG2
RE
FE
OMSK
CL2/2
CL2/1
T2D1, 0
DCG
Manchester
modulator
Biphase/
4-bit compare
8-bit compare
4-bit counter
8-bit counter
4-bit register
8-bit register
T2M2
RES
RES
T2OS2, 1, 0
OVF2
CM2
CM1
T2RM
S1
RES/SET
T2OTM
Toggle
T2TOP
and T2OTM-bit
output mode
M2
Timer 2
M2
S2
T2IM
T2CTM
Modulator3
S3
T2O
4551C–4BMCU–01/04
DCGO
TOG2
INT4
POUT