MCP79410T-I/MNY Microchip Technology, MCP79410T-I/MNY Datasheet - Page 16

• Manufacturer Part Number: MCP79410T-I/MNY
• Description: IC RTC/CALENDER 8TDFN
• Manufacturer: Microchip Technology
• Type: Clock/Calendar/EEPROMr

Specifications of MCP79410T-I/MNY

• Package / Case: 8-WFDFN Exposed Pad
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Memory Size: 1K (128 x 8)
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Function: Clock/Calendar
• Rtc Memory Size: 64 B
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Rtc Bus Interface: I2C
• Supply Current: 400 uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: MCP79410T-I/MNYTR

MCP7941X
5.0
The MCP7941X has both on-board EEPROM memory
and Battery-Backed SRAM. The SRAM is arranged as
64 x 8 bytes and is retained when the V
5.1
FIGURE 5-1:
FIGURE 5-2:
The 64 bytes of user SRAM are at location 0x20h and
can be accessed during an RTCC update. Upon POR
the SRAM will be in an undefined state.
Writing to the SRAM and RTCC is accomplished in a
similar way to writing to the EEPROM (as described
later in this document) with the following consider-
ations:
• There is no page. The entire 64 bytes of SRAM or
• The SRAM allows an unlimited number of read/
• The RTCC and SRAM are not accessible when
• The RTCC and SRAM are separate blocks. The
• Read and write access is limited to either the
• Data written to the RTCC and SRAM are on a per
DS22266A-page 16
32 bytes of RTCC register can be written in one
command.
write cycles with no cell wear out.
the device is running on the external V
SRAM array may be accessed during an RTCC
update.
RTCC register block or the SRAM array. The
Address Pointer will rollover to the start of the
addressed block.
byte basis.
ON BOARD MEMORY
SRAM
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
SRAM/RTCC BYTE WRITE
SRAM/RTCC MULTIPLE BYTE WRITE
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S 1 1 0 1
CONTROL
BYTE
1 1 1
BAT
S 1 1 0 1
S
T
A
R
T
CC
0
.
supply is
A
C
K
CONTROL
x
BYTE
ADDRESS
Preliminary
1 1 1
BYTE
0
A
C
K
x
ADDRESS
A
C
K
removed, provided the V
enabled. The EEPROM is organized as 128 x 8 bytes.
The EEPROM is nonvolatile memory and does not
require the V
BYTE
Note:
DATA BYTE 0
Entering an address past 5F for an SRAM
operation will result in the MCP7941X not
acknowledging the address.
BAT
A
C
K
supply for retention.
A
C
K
DATA
 2010 Microchip Technology Inc.
DATA BYTE N
BAT
A
C
K
supply is present and
S
T
O
P
P
A
C
K
S
T
O
P
P