SST25VF020-20-4C-SAE Microchip Technology, SST25VF020-20-4C-SAE Datasheet
SST25VF020-20-4C-SAE
Specifications of SST25VF020-20-4C-SAE
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SST25VF020-20-4C-SAE Summary of contents
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... Mbit SPI Serial Flash SST25VF020 / 0402Mb / 4Mb Serial Peripheral Interface (SPI) flash memory FEATURES: • Single 2.7-3.6V Read and Write Operations • Serial Interface Architecture – SPI Compatible: Mode 0 and Mode 3 • 20 MHz Max Clock Frequency • Superior Reliability – Endurance: 100,000 Cycles (typical) – ...
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... Data Sheet Address Buffers and Latches CE# FIGURE 1: Functional Block Diagram ©2006 Silicon Storage Technology, Inc Decoder Control Logic Serial Interface SCK SI SO WP# HOLD Mbit SPI Serial Flash SST25VF020 SuperFlash Memory Y - Decoder I/O Buffers and Data Latches 1231 B1.0 S71231-07-000 10/06 ...
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... Mbit SPI Serial Flash SST25VF020 PIN DESCRIPTION CE Top View WP 1231 08-soic P1.0 8- SOIC LEAD FIGURE 2: Pin Assignments TABLE 1: Pin Description Symbol Pin Name Functions SCK Serial Clock To provide the timing of the serial interface. Commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input ...
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... BFH Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). 43H The SST25VF020 supports both Mode 0 (0,0) and Mode 3 T2.0 1231 (1,1) of SPI bus operations. The difference between the two modes, as shown in Figure 3, is the state of the SCK signal when the bus master is in Stand-by mode and no data is being transferred ...
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... HOLD# Active FIGURE 4: Hold Condition Waveform Write Protection SST25VF020 provides software Write protection. The Write Protect pin (WP#) enables or disables the lock-down function of the status register. The Block-Protection bits (BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status register. See Table 5 for Block-Protection description ...
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... Mbit SPI Serial Flash Program operation, the status register may be read only to determine the completion of an operation in progress. Table 4 describes the function of each bit in the software status register. Default at Power- SST25VF020 Read/Write R R R/W R/W N/A R R/W T4.0 1231 S71231-07-000 10/06 ...
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... Mbit SPI Serial Flash SST25VF020 Block Protection (BP1, BP0) The Block-Protection (BP1, BP0) bits define the size of the memory area, as defined in Table software pro- tected against any memory Write (Program or Erase) operations. The Write-Status-Register (WRSR) instruction is used to program the BP1 and BP0 bits as long as WP# is high or the Block-Protect-Lock (BPL) bit is 0 ...
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... Data Sheet Instructions Instructions are used to Read, Write (Erase and Program), and configure the SST25VF020. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, or Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed first ...
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... Mbit SPI Serial Flash SST25VF020 Read The Read instruction outputs the data starting from the specified address location. The data output stream is con- tinuous through all addresses until terminated by a low to high transition on CE#. The internal address pointer will automatically increment until the highest memory address is reached ...
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... Latch bit (WEL = 0 A[7:0] Data Byte Write Disable (WRDI) Instruction to terminate AAI Operation 10 2 Mbit SPI Serial Flash SST25VF020 for the completion of each inter Data Byte 2 05 Read Status Register (RDSR) Instruction to verify end of AAI Operation D OUT 1231 F06.1 S71231-07-000 10/06 ...
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... Mbit SPI Serial Flash SST25VF020 Sector-Erase The Sector-Erase instruction clears all bits in the selected 4 KByte sector to FFH. A Sector-Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of the any command sequence ...
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... Status-Register is continuous with ongoing clock cycles until it is terminated by a low to high transition of the CE#. See Figure 11 for the RDSR instruction sequence Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB 12 2 Mbit SPI Serial Flash SST25VF020 Status 1231 F10.1 Register Out S71231-07-000 for CE 10/06 ...
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... Mbit SPI Serial Flash SST25VF020 Write-Enable (WREN) The Write-Enable (WREN) instruction sets the Write- Enable-Latch bit to 1 allowing Write operations to occur. The WREN instruction must be executed prior to any Write (Program/Erase) operation. CE# must be driven high before the WREN instruction is executed. FIGURE 12: Write Enable (WREN) Sequence ...
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... WP# and BPL functions. CE# must be driven low before the command sequence of the WRSR instruction is entered and driven high before the WRSR instruction is executed. See Figure 14 for EWSR and WRSR instruction sequences MODE 3 MODE 0 STATUS REGISTER MSB MSB HIGH IMPEDANCE 14 SST25VF020 1231 F13.1 S71231-07-000 10/06 ...
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... Mbit SPI Serial Flash SST25VF020 Read-ID The Read-ID instruction identifies the device as SST25VF020 and manufacturer as SST. The device infor- mation can be read from executing an 8-bit command, 90H or ABH, followed by address bits [A Read-ID instruction, the manufacturer’ located in CE# MODE MODE 0 SCK ...
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... CE#=0 CE#= µA CE#= µA V =GND µA V =GND to V OUT =100 µ -0 =-100 µ Mbit SPI Serial Flash SST25VF020 +0.5V DD +2. EST = /0.9 V @20 MHz, SO=open Max Max Min Max =V Min Min DD DD T7.0 1231 Minimum Units 10 µs 10 µs T8.0 1231 ...
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... Mbit SPI Serial Flash SST25VF020 TABLE 10: Reliability Characteristics Symbol Parameter 1 N Endurance END 1 T Data Retention Latch Up LTH 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 11: AC Operating Characteristics V Symbol Parameter ...
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... FIGURE 16: Serial Input Timing Diagram CE# T SCKH SCK T CLZ SO SI FIGURE 17: Serial Output Timing Diagram ©2006 Silicon Storage Technology, Inc. T SCKF T SCKR T SCKL T OH MSB Mbit SPI Serial Flash SST25VF020 T CPH T T CHS CEH LSB HIGH-Z 1231 F15.0 T CHZ LSB 1231 F16.0 S71231-07-000 10/06 ...
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... Mbit SPI Serial Flash SST25VF020 CE# SCK SO SI HOLD# FIGURE 18: Hold Timing Diagram Max DD Chip selection is not allowed. All commands are rejected by the device. V Min DD FIGURE 19: Power-up Timing Diagram ©2006 Silicon Storage Technology, Inc HHH HLS T HLH PU-READ Device fully accessible T PU-WRITE ...
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... V (0.1V DD ILT DD ) and V (0.3V ). Input rise and fall times (10 TESTER TO DUT 20 2 Mbit SPI Serial Flash SST25VF020 V HT OUTPUT V LT 1231 F19.1 ) for a logic “0”. Measurement reference points ↔ 90%) are <5 ns. Note Test HT HIGH Test ...
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... Device Speed Suffix1 SST25VFXXX - XXX - XX Valid combinations for SST25VF020 SST25VF020-20-4C-SAE SST25VF020-20-4C-QAE SST25VF020-20-4I-SAE SST25VF020-20-4I-QAE SST25VF020-20-4E-SAE SST25VF020-20-4E-QAE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ...
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... FIGURE 22: 8-lead Small Outline Integrated Circuit (SOIC) 150 mil body width (4.9mm x 6mm) SST Package Code: SA ©2006 Silicon Storage Technology, Inc. 2 Mbit SPI Serial Flash SIDE VIEW 7° 4 places 0.51 0.33 1.27 BSC END VIEW 45° 0.25 0.10 1.75 0.25 1.35 0.19 08-soic-5x6-SA-8 22 SST25VF020 7° 4 places 0° 8° 1.27 0.40 1mm S71231-07-000 10/06 ...
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... Mbit SPI Serial Flash SST25VF020 TOP VIEW Pin #1 Corner 6.00 ± 0.10 Note: 1. All linear dimensions are in millimeters (max/min). 2. Untoleranced dimensions (shown with box surround) are nominal target dimensions. 3. The external paddle is electrically connected to the die back-side and possibly to certain V This paddle can be soldered to the PC board; ...