PIC18LF24K22-I/SS Microchip Technology, PIC18LF24K22-I/SS Datasheet - Page 337
![IC PIC MCU 16KB FLASH 28SSOP](/photos/19/6/190632/4696165_sml.jpg)
PIC18LF24K22-I/SS
Manufacturer Part Number
PIC18LF24K22-I/SS
Description
IC PIC MCU 16KB FLASH 28SSOP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18LF24K22-I/SS
Core Size
8-Bit
Program Memory Size
16KB (8K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 19x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP (0.200", 5.30mm Width)
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
256Byte
Ram Memory Size
768Byte
Cpu Speed
64MHz
No. Of Timers
7
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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TABLE 20-1:
REGISTER 20-1:
2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-4
bit 3
bit 2
bit 1
bit 0
Note 1:
SRCLK<2:0>
SRLEN
R/W-0
111
110
101
100
011
010
001
000
2:
Changing the SRCLK bits while the SR latch is enabled may cause false triggers to the set and Reset
inputs of the latch.
Set only, always reads back ‘0’.
SRLEN: SR Latch Enable bit
1 = SR latch is enabled
0 = SR latch is disabled
SRCLK<2:0>: SR Latch Clock Divider Bits
000 = Generates a 2 T
001 = Generates a 2 T
010 = Generates a 2 T
011 = Generates a 2 T
100 = Generates a 2 T
101 = Generates a 2 T
110 = Generates a 2 T
111 = Generates a 2 T
SRQEN: SR Latch Q Output Enable bit
1 = Q is present on the SRQ pin
0 = Q is internal only
SRNQEN: SR Latch Q Output Enable bit
1 = Q is present on the SRNQ pin
0 = Q is internal only
SRPS: Pulse Set Input of the SR Latch bit
1 = Pulse set input for 2 T
0 = No effect on set input
SRPR: Pulse Reset Input of the SR Latch bit
1 = Pulse reset input for 2 T
0 = No effect on Reset input
DIVSRCLK FREQUENCY TABLE
Divider
R/W-0
512
256
128
64
32
16
8
4
SRCON0: SR LATCH CONTROL REGISTER
SRCLK<2:0>
F
W = Writable bit
‘1’ = Bit is set
OSC
R/W-0
25.6 s
12.8 s
6.4 s
3.2 s
1.6 s
0.8 s
0.4 s
0.2 s
= 20 MHz
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
wide pulse on DIVSRCLK every 4 peripheral clock cycles
wide pulse on DIVSRCLK every 16 peripheral clock cycles
wide pulse on DIVSRCLK every 32 peripheral clock cycles
wide pulse on DIVSRCLK every 64 peripheral clock cycles
wide pulse on DIVSRCLK every 128 peripheral clock cycles
wide pulse on DIVSRCLK every 256 peripheral clock cycles
wide pulse on DIVSRCLK every 512 peripheral clock cycles
(1)
wide pulse on DIVSRCLK every 8 peripheral clock cycles
clock cycles
R/W-0
clock cycles
F
Preliminary
OSC
0.25 s
0.5 s
32 s
16 s
8 s
4 s
2 s
1 s
= 16 MHz
(2)
U = Unimplemented
‘0’ = Bit is cleared
(2)
SRQEN
R/W-0
PIC18(L)F2X/4XK22
F
OSC
0.5 s
64 s
32 s
16 s
8 s
4 s
2 s
1 s
= 8 MHz F
SRNQEN
R/W-0
OSC
128 s
C = Clearable only bit
x = Bit is unknown
64 s
32 s
16 s
8 s
4 s
2 s
1 s
= 4 MHz
R/W-0
SRPS
DS41412A-page 337
F
OSC
512 s
256 s
128 s
64 s
32 s
16 s
R/W-0
SRPR
8 s
4 s
= 1 MHz
bit 0
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