PIC18F24K22-I/ML Microchip Technology, PIC18F24K22-I/ML Datasheet - Page 126
PIC18F24K22-I/ML
Manufacturer Part Number
PIC18F24K22-I/ML
Description
IC PIC MCU 16KB FLASH 28QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC18F26J13-ISS.pdf
(496 pages)
3.PIC18F24K22-ISP.pdf
(494 pages)
Specifications of PIC18F24K22-I/ML
Core Size
8-Bit
Program Memory Size
16KB (8K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 19x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
256Byte
Ram Memory Size
768Byte
Cpu Speed
64MHz
No. Of Timers
7
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F24K22-I/ML
Manufacturer:
MINI
Quantity:
2 001
Part Number:
PIC18F24K22-I/ML
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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PIC18(L)F2X/4XK22
REGISTER 9-12:
REGISTER 9-13:
DS41412D-page 126
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-3
bit 2
bit 1
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-3
bit 2
bit 1
bit 0
U-0
U-0
—
—
Unimplemented: Read as ‘0’
CCP5IE: CCP5 Interrupt Enable bit
1 = Enabled
0 = Disabled
CCP4IE: CCP4 Interrupt Enable bit
1 = Enabled
0 = Disabled
CCP3IE: CCP3 Interrupt Enable bit
1 = Enabled
0 = Disabled
Unimplemented: Read as ‘0’
TMR6IE: TMR6 to PR6 Match Interrupt Enable bit
1 = Enables the TMR6 to PR6 match interrupt
0 = Disables the TMR6 to PR6 match interrupt
TMR5IE: TMR5 Overflow Interrupt Enable bit
1 = Enables the TMR5 overflow interrupt
0 = Disables the TMR5 overflow interrupt
TMR4IE: TMR4 to PR4 Match Interrupt Enable bit
1 = Enables the TMR4 to PR4 match interrupt
0 = Disables the TMR4 to PR4 match interrupt
U-0
U-0
—
—
PIE4: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 4
PIE5: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 5
W = Writable bit
W = Writable bit
‘1’ = Bit is set
‘1’ = Bit is set
U-0
U-0
—
—
U-0
U-0
Preliminary
—
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
U-0
—
—
CCP5IE
TMR6IE
R/W-0
R/W-0
2010 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
CCP4IE
TMR5IE
R/W-0
R/W-0
CCP3IE
TMR4IE
R/W-0
R/W-0
bit 0
bit 0
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